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3D NAND memory and manufacturing method thereof

A 3D NAND and manufacturing method technology, applied in the direction of electric solid-state devices, semiconductor devices, electrical components, etc., can solve the difficulty in controlling the thickness of the back selection gate oxide, the increase in the difficulty of etching the stacked structure, the uniformity of the epitaxial structure, and continuity defects, etc. question

Active Publication Date: 2020-09-04
YANGTZE MEMORY TECH CO LTD
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  • Summary
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  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The traditional method of realizing the communication between the channel structure and the substrate usually faces the problem of the uniformity and continuity of the epitaxial structure, or the difficulty of controlling the thickness of the back selection gate oxide.
In the multi-layer trench hole process, it will also face the problem of increased etching difficulty of the stacked structure

Method used

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  • 3D NAND memory and manufacturing method thereof
  • 3D NAND memory and manufacturing method thereof
  • 3D NAND memory and manufacturing method thereof

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Experimental program
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Embodiment 1

[0117] This embodiment provides a method for manufacturing a 3D NAND memory, such as figure 2 As shown, the method includes the following steps:

[0118] Step S101: providing a substrate, and forming a stacked structure on the substrate, the stacked structure including alternately stacked sacrificial layers and insulating layers;

[0119] refer to image 3 Firstly, a substrate 100 is provided, and a stack structure 102 is formed on the substrate 100 . In this embodiment, the substrate 100 may be a substrate of silicon, single crystal silicon-on-insulator or other suitable materials. Moreover, a P-type well on the top of the substrate 100 and an N-type well below the P-type well (not shown in detail) may also be formed in the substrate 100 . The stacked structure 102 may have 64 layers, 96 layers, 128 layers or even more layers.

[0120] still refer to image 3When forming the stacked structure 102 above, the bottom sacrificial layer 101 is firstly formed on the substrate...

Embodiment 2

[0141] This embodiment provides a 3D NAND memory, which can also refer to Figure 3 ~ Figure 17 , the memory consists of:

[0142] a substrate; a stack structure formed above the substrate, the stack structure comprising a source layer formed on the substrate, a first isolation layer formed above the source layer, and a first isolation layer formed on the first alternately stacked gate layers and insulating layers over an isolation layer;

[0143] a channel structure running through the stack structure;

[0144] a common source, the common source runs through the stack structure and communicates with the substrate;

[0145] Wherein, the source layer includes a first portion located below the stack structure and a second portion formed in the channel structure and communicated with the channel structure, and, in the stacking direction of the stack structure, The width of the second portion is greater than the width of the first portion.

[0146] refer to Figure 3 ~ Figure...

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Abstract

The invention provides a 3D NAND memory and a manufacturing method thereof. According to the method, a stacked structure comprising a bottom sacrificial layer, sacrificial layers and insulating layersis formed on a substrate, the sacrificial layers and the insulating layers are alternately stacked on the bottom sacrificial layer, the bottom sacrificial layer is replaced with a source electrode layer, oxidation treatment is conducted on the source electrode layer, a first isolation layer is formed on the surface of the source electrode layer, and the function of selecting gate oxide on the back is achieved. The method facilitates control over thickness of the first isolation layer and improves the uniformity of the first isolation layer, so that uniform inversion of the source electrode layer is facilitated, and an electronic channel is ensured in read-write operation of the memory. The problems in the thickness and uniformity of the source electrode layer caused by the thickness problem of the back selection gate oxide layer are solved, and the continuity of a P-type trap and supply of holes in the erasing process can be realized. The source electrode layer is formed in the channel structure in the stacking direction at the same time, the contact area of the source electrode layer and the channel layer is increased, and electrical connection between the source electrode layerand the channel layer is enhanced.

Description

technical field [0001] The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a 3D NAND memory and a manufacturing method thereof. Background technique [0002] As the feature size of devices in integrated circuits continues to shrink, 3D memory technologies that stack multiple planes of memory cells to achieve greater storage capacity and lower cost per bit are increasingly favored. 3D memory is a technology for stacking data units. Currently, more than 32 layers, or even 72, 96, 128 or more layers of data units can be stacked. As the number of stacked layers increases, the lead-out of the memory structure that runs through the stacked structure faces increasing challenges. [0003] The traditional method of realizing the communication between the channel structure and the substrate usually faces the problem of defects in the uniformity and continuity of the epitaxial structure, or the difficulty in controlling the thickness ...

Claims

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Application Information

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IPC IPC(8): H01L27/1157H01L27/11582
CPCH10B43/35H10B43/27
Inventor 孙中旺夏志良王迪周文犀
Owner YANGTZE MEMORY TECH CO LTD
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