3D NAND memory and manufacturing method thereof
A 3D NAND and manufacturing method technology, applied in the direction of electric solid-state devices, semiconductor devices, electrical components, etc., can solve the difficulty in controlling the thickness of the back selection gate oxide, the increase in the difficulty of etching the stacked structure, the uniformity of the epitaxial structure, and continuity defects, etc. question
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Embodiment 1
[0117] This embodiment provides a method for manufacturing a 3D NAND memory, such as figure 2 As shown, the method includes the following steps:
[0118] Step S101: providing a substrate, and forming a stacked structure on the substrate, the stacked structure including alternately stacked sacrificial layers and insulating layers;
[0119] refer to image 3 Firstly, a substrate 100 is provided, and a stack structure 102 is formed on the substrate 100 . In this embodiment, the substrate 100 may be a substrate of silicon, single crystal silicon-on-insulator or other suitable materials. Moreover, a P-type well on the top of the substrate 100 and an N-type well below the P-type well (not shown in detail) may also be formed in the substrate 100 . The stacked structure 102 may have 64 layers, 96 layers, 128 layers or even more layers.
[0120] still refer to image 3When forming the stacked structure 102 above, the bottom sacrificial layer 101 is firstly formed on the substrate...
Embodiment 2
[0141] This embodiment provides a 3D NAND memory, which can also refer to Figure 3 ~ Figure 17 , the memory consists of:
[0142] a substrate; a stack structure formed above the substrate, the stack structure comprising a source layer formed on the substrate, a first isolation layer formed above the source layer, and a first isolation layer formed on the first alternately stacked gate layers and insulating layers over an isolation layer;
[0143] a channel structure running through the stack structure;
[0144] a common source, the common source runs through the stack structure and communicates with the substrate;
[0145] Wherein, the source layer includes a first portion located below the stack structure and a second portion formed in the channel structure and communicated with the channel structure, and, in the stacking direction of the stack structure, The width of the second portion is greater than the width of the first portion.
[0146] refer to Figure 3 ~ Figure...
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