Hardware architecture for accelerating Deep Q-Network algorithm and design space exploration method of hardware architecture
A hardware architecture and algorithm technology, applied in the field of artificial intelligence, can solve problems such as optimization of FPGA hardware computing architecture, high computational complexity, and large consumption of storage resources.
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[0036] A kind of hardware framework for accelerating Deep Q-Network algorithm, described hardware framework comprises general processor module and FPGA programmable logic module and external DDR memory, and described FPGA programmable logic module comprises AXI bus interface, Target Q module, Current Q module, Loss calculation module, mode control module, parameter storage unit and weight update unit;
[0037] The general processor module is responsible for interacting with the external environment and realizing the calculation of the reward function, and is also responsible for the maintenance of the DeepQ-Network algorithm experience pool;
[0038] The external DDR memory is mainly responsible for the storage of the Deep Q-Network algorithm experience pool.
[0039] The AXI bus interface is a general AXI bus interface structure, which is responsible for realizing the transmission and feedback of control signals and data signals between the general processor and the FPGA prog...
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