AXI-Stream interface write control circuit and method

Abstract

The invention discloses an AXI-Stream interface write control circuit. The system comprises a main control state machine, a three-level multiplexer sel signal control logic device, a three-level clockenabling control logic device, a four-level D trigger and a three-level multiplexer. The output end of the main control state machine is connected with the three-level multiplexer sel signal controllogic device and the three-level clock enabling control logic device and used for outputting a tvalid signal to an AXI port. The three-stage clock enabling control logic devices are respectively usedfor receiving the treading signals of the AXI ports and are respectively connected with the corresponding next-stage D triggers; the output end of each stage of D trigger is connected with the first input end of the corresponding multiplexer, and the output end of each stage of multiplexer is connected with the input end of the corresponding next stage of D trigger; the invention further disclosesan AXI-Stream interface write control method. According to the circuit, the logic resource utilization rate in the mechanism FPGA is extremely high, and all output signals are output by the D trigger, so that the time sequence performance is improved, and the time sequence convergence is facilitated.

Description

technical field [0001] The invention belongs to the technical field of data transmission, and in particular relates to an AXI-Stream interface write control circuit and method. Background technique [0002] Most of the data transmission interfaces of FPGA IP cores provided by Xilinx are AXI interfaces. Among them, AXI-Stream is widely used when transmitting large blocks of continuous data. Generally, the write control of AXI interfaces is to directly use the tready of the AXI data sending port as The enable signal directly requests data from the data source, and after the data is requested, the user pulls the tvalid signal high to write data to the AXI data sending port, but one problem faced by this method is that when the tready signal is pulled low during transmission , there will be a set of data that cannot be written into the AXI send port, so a set of flip-flops are required to register the data, and when tready is high again, it generally requires a delay of one cloc...

AI Technical Summary

Problems solved by technology

[0002] Most of the data transmission interfaces of FPGA IP cores provided by Xilinx are AXI interfaces. Among them, AXI-Stream is widely used when transmitting large blocks of continuous data. Generally, the write control of AXI interfaces is to directly use the tready of the AXI data sending port as The enable signal directly requests data from the data source, and after the data is requested, the user pulls the tvalid signal high to write data to the AXI data sending port, but one problem faced by this method is that when the tready signal is pulled low during transmission , there will be a set of data that cannot be written into the AXI send port, so a set of flip-flops are required to register the data, and when tready is high again, it generally requires a delay of one clock cycle, and the data is output from the combinatorial logic to the AXI interface, which will face Timing Closure Issues

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