Semiconductor structure and forming method thereof

Abstract

The embodiment of the invention relates to a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a wafer stacking structure to be cut; performing first cutting processing on the wafer stacking structure, forming a first through hole in the cutting channel, and extending the first through hole to form a first extending pattern in the direction perpendicular to the first surface and the extending direction of the cutting channel; performing second cutting treatment on the cutting channel at the bottom of the first through hole, cutting the wafer stacking structure until the wafer stacking structure is cut through; forming a second through hole in the cutting channel through second cutting treatment; in the direction perpendicularto the first face and the extending direction of the cutting channel, enabling the second through hole to extend to form a second extending pattern, wherein the second extending pattern and the firstextending pattern have an overlapping part, and the width of the overlapping part is less than the width of the first through hole and the width of the second through hole. According to the invention,the cutting of the wafer stacking structure can be effectively realized, and mistaken cutting of the chip is avoided.

Description

technical field [0001] Embodiments of the present invention relate to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background technique [0002] In recent years, as semiconductor devices continue to respond to the demand for "faster, cheaper, and smaller", three-dimensional stacked 3D packaging technology has entered mainstream semiconductor manufacturing. Among them, TSV (Through Silicon Via) technology is interconnected through vertical chip vias, which brings shorter interconnection length and smaller packaging area, greatly improves signal transmission speed and reduces parasitic power consumption. [0003] The existing method for forming a three-dimensional stacked 3D packaging structure generally includes: stacking and bonding a plurality of wafers in a direction perpendicular to the surface of the wafer; after that, cutting the bonded plurality of wafers along a wafer dicing line , to obtain ...

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Problems solved by technology

[0004] However, the performance of the 3D packaging structure

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