A verification method of static random access memory based on random binary sequence

Abstract

A static random access memory verification method based on random binary sequence, first calculate the device parameters such as SRAM memory address bit width and data bit width; then generate SRAM memory write operation address; use positive random binary sequence and inverse random binary sequence to SRAM The memory is verified, the statistical results are analyzed, and the functional test of the SRAM memory is completed. The invention uses random binary sequences to control the read and write operations of the SRAM memory, simulates the read address and data under application conditions, enhances the fit between the memory test verification and the application conditions, and at the same time can verify the bandwidth capability of the memory under high-speed application conditions. Completeness of memory functional verification.

Description

technical field [0001] The invention relates to a method for verifying a static random access memory based on a random binary sequence, and belongs to the technical field of functional testing and verification of digital integrated circuits. Background technique [0002] Static random access memory SRAM is mainly used in the periphery of the processor as a data cache space, and is characterized by a fast speed. [0003] The high-speed characteristics of SRAM make SRAM memory suitable for the main memory of processors and are widely used in industrial electronics, instrumentation, and aerospace. Memory is an important component in electronic systems and one of the most commonly used components in the field of electronic information, so the verification of SRAM memory is very important. [0004] Inside the memory device is a regular array of memory cells, as well as a large number of logic devices, such as control circuits, sensitive amplifiers and read circuits, all of which...

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Problems solved by technology

[0008] The commonly used SRAM memory verification methods in the above concentration all use regular test patterns to verify the read and write of SRAM memory, but the actual application read and write patterns are more complicated, so the test patterns in SRAM memory verification are different from actual applications. difference

At the same time, with the continuous improvement of the working speed of SRAM memory, the bandwidth of the signal transmission capability of the read-write timing link inside the SRAM memory also needs to be verified. The existing verification methods generally use regular code patterns to verify the data storage of the SRAM memory storage unit. , unable to verify the signal transmission bandwidth of read and write timing links

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