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Method and system for self-adaptive subdivision of polygonal unstructured grid for integrated circuit layout

A technology of unstructured grids and integrated circuits, applied in CAD circuit design, image data processing, special data processing applications, etc., can solve problems such as too dense grids

Active Publication Date: 2020-12-01
北京智芯仿真科技有限公司
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Problems solved by technology

[0010] The purpose of the present invention is to provide a method and system for self-adaptive subdivision of polygonal unstructured grids of integrated circuit layout, to solve the problem that the grids generated in some local areas are too dense in the existing grid subdivision technology, and then It can improve the efficiency of numerical calculation and reduce the calculation memory while improving the accuracy of grid division

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  • Method and system for self-adaptive subdivision of polygonal unstructured grid for integrated circuit layout
  • Method and system for self-adaptive subdivision of polygonal unstructured grid for integrated circuit layout

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[0074] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0075] The purpose of the present invention is to provide a method and system for self-adaptive subdivision of polygonal unstructured grids in integrated circuit layouts, to solve the problem in the prior art that the grids generated in some local areas are too dense, and to improve the network While improving the grid subdivision accuracy, the numerical calculation efficiency is improved and the calculation memory is reduced.

[0076] In order to make the abo...

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Abstract

The invention relates to a method and system for self-adaptive subdivision of a polygonal unstructured grid of an integrated circuit layout. The method includes sequentially inserting eccentric points into the existing mesh according to the lost and eroded polygon edges to recover the lost and eliminated eroded polygon edges, determining the triangles to be subdivided according to the set ratio / minimum angle threshold, in order Insert the center of the eccentric circle of the triangle to be subdivided into the existing mesh to eliminate the triangle to be subdivided. The above restores the lost and eliminated the eroded polygon edges and eliminates the triangle to be subdivided. Interleaved until the integrated circuit layout polygonal unstructured network There are no missing and eroded polygon edges and triangles to be subdivided in the grid, and finally form a new unstructured grid of VLSI layout to solve the redundancy caused by newly inserted nodes in the prior art While solving the problem of excessively dense local grids, it improves grid division accuracy and numerical calculation efficiency, and reduces calculation memory.

Description

technical field [0001] The invention relates to the field of unstructured grid subdivision of circuit layout, in particular to a method and system for self-adaptive subdivision of polygonal unstructured grid of integrated circuit layout. Background technique [0002] Unstructured meshing of multilayer VLSI layout is the basis of numerical calculation of electromagnetic fields for integrated circuit back-end verification. In order to accurately analyze the power integrity and signal integrity of VLSI, it is necessary to use strict numerical calculation methods to calculate the distribution of electromagnetic fields in integrated circuits. The accuracy of numerical calculation of electromagnetic fields depends largely on the discreteness of the calculation field , that is, the quality of grid division in the calculation field, and the number of generated grid nodes also directly determines the accuracy and speed of numerical calculation. For integrated circuits with increasin...

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F30/39G06T17/20
CPCG06T17/20G06F30/39
Inventor 唐章宏邹军汲亚飞王芬黄承清
Owner 北京智芯仿真科技有限公司
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