A method for reducing annealing thermal stress of heterostructure thin film

Abstract

The invention relates to the technical field of semiconductors, and discloses a method for reducing the annealing thermal stress of a heterostructure thin film. The specific steps of the method are as follows: providing a heterogeneous substrate and a supporting substrate; bonding the heterogeneous substrate and the supporting substrate through a low thermal conductivity medium to form a dielectric layer bonding substrate; bonding the dielectric layer The combined substrate is placed in an annealing furnace for annealing, the annealing curve of the heterogeneous substrate satisfies the first preset formula, and the annealing curve of the support substrate satisfies the second preset formula, so that the annealing curve of the heterogeneous substrate when annealing The amount of thermal expansion is equal to the amount of thermal expansion when the supporting substrate is annealed. The above-mentioned method for reducing the annealing thermal stress of the heterogeneous structure thin film provided by the present invention has the characteristics of reducing the annealing thermal stress of the thin film, thereby improving the bonding force between different substrates and the quality of the thin film.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a method for reducing the annealing thermal stress of a heterostructure thin film. Background technique [0002] In the past few decades, microelectronics technology has continued the development trend of Moore's Law, using reduced device feature size and increased integration to continuously improve performance, efficiency and reduce system cost. However, with the innovation of emerging technologies such as 5G and AI, , and the emergence of new applications such as AR / VR, which put forward higher requirements for system functions, power consumption, memory calculation and operating speed, and promote the development of microelectronics technology, making the size of transistors from 45nm in 2007 Shrinking to less than 10nm today, the size of transistors has gradually approached the physical limit, facing the challenges of short channel effects, increased gate leakage, and...

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Problems solved by technology

[0002] In the past few decades, microelectronics technology has continued the development trend of Moore's Law, using reduced device feature size and increased integration to continuously improve performance, efficiency and reduce system cost. However, with the innovation of emerging technologies such as 5G and AI, , and the emergence of new applications such as AR / VR, which put forward higher requirements for system functions, power consumption, memory calculation and operating speed, and promote the development of microelectronics technology, making the size of transistors from 45nm in 2007 Shrinking to less than 10nm today, the size of transistors has gradually approached the physical limit, facing the challenges of short channel effects, increased gate leakage and increased power consumption

[0003] At present, how to integrate different functions together to achieve high-efficiency and low-cost systems to overcome the size limit of transistors has become a research hotspot. Specifically, hetero-epitaxy is often used in the prior art, but its Limited by the lattice mismatch and crystal form mismatch between different materials, it is difficult to achieve high-quality heteroepitaxial substrates

[0004] Then, the emergence of bonding technology, which can avoid problems such as lattice mismatch and crystal form mismatch in heteroepitaxy, but due to the high temperature of bonding, annealing and exfoliation transfer, it is easy to introduce Thermal stress, leading to debonding or even splitting

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