Device and method for executing matrix addition/subtraction operation

Abstract

The invention provides a device for executing matrix addition and subtraction operation, and the device is characterized in that the device comprises: a storage unit which is used for storing matrix data related to a matrix operation instruction; the register unit that is used for storing scalar data related to the matrix operation instruction; the control unit that is used for decoding the matrixoperation instruction and controlling the operation process of the matrix operation instruction; the matrix operation unit that is used for carrying out matrix addition and subtraction operation on an input matrix according to the decoded matrix operation instruction, wherein the matrix operation unit is a customized hardware circuit. The invention further provides a method for executing matrix addition and subtraction.

Description

technical field [0001] The present disclosure relates to the field of computers, and in particular to a device and method for performing matrix addition and subtraction operations. Background technique [0002] In the current computer field, with the maturity of emerging technologies such as big data and machine learning, more and more tasks include various matrix addition and subtraction operations, especially the addition and subtraction of large matrices, which often become The bottleneck of algorithm speed and effect improvement. , [0003] In the prior art, a known solution for matrix addition and subtraction is to use a general-purpose processor, which executes general-purpose instructions through a general-purpose register file and general-purpose functional units to perform matrix addition and subtraction. However, one of the disadvantages of this method is that a single general-purpose processor is mostly used for scalar calculations, and the calculation performan...

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Problems solved by technology

However, according to this method, the existing special-purpose matrix operation device is limited by the design of the register file, and cannot flexibly support matrix addition and subtraction operations of different lengths

[0006] In summary, the existing multi-core general-purpose processors on-chip, inter-chip interconnection general-purpose processors (single-core or multi-core), or inter-chip interconnection graphics processors cannot perform efficient matrix addition and subtraction operations, and these existing When dealing with matrix addition and subtraction operations, some technologies have problems such as large code volume, limited inter-chip communication, insufficient on-chip cache, and insufficient flexibility in the size of the supported matrix.

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