Method and device for controlling erasure performance

Abstract

The invention provides a method and a device for controlling erasure performance. The method is applied to an NOR flash memory. The NOR flash memory comprises a NOR flash memory and a NOR flash memory, the system comprises a temperature sensor, a clock frequency generator, an erase operation state machine and an erase storage unit, the erase operation state machine includes: an erase operation state machine; a counter, the method comprising: a counter; the erasing operation state machine receives an erasing operation instruction; and executing an erase verification operation and an erase pressurization operation according to the erase operation instruction, the erase pressurization operation comprising: receiving the working temperature of the NOR flash memory sent by the temperature sensor, adjusting the time of a single erase pressurization operation according to the working temperature, and completing the erase pressurization operation according to the adjusted time. When the erasepressurization operation is executed, the erase operation state machine adjusts the time of the single erase pressurization operation according to the working temperature of the NOR flash memory, completes the erase pressurization operation, controls the cycle period of the erase verification operation and the erase pressurization operation, and improves the erase performance of the NOR flash memory.

Description

Technical field [0001] The present invention relates to the storage field, in particular to a method and device for controlling erasing performance. Background technique [0002] At present, NOR flash memory uses tunneling to realize the erasing operation. The research results show that as the temperature decreases, the electron activity will also decrease, which makes it difficult for electrons to tunnel from the floating gate layer through the tunnel oxide layer during erasing. Substrate, causing the erase time to increase. [0003] Reference figure 1 , Shows a schematic diagram of the erasing principle of the existing NOR flash memory. When performing the erasing operation, in order to make the electrons tunnel from the floating gate layer to the substrate, a negative voltage needs to be applied to the gate terminal (G) and the substrate is positive The drain terminal (D) and source terminal (S) are left floating. Studies have shown that the longer the erasing pressure, the bet...

AI Technical Summary

Problems solved by technology

[0005] The invention provides a method and device for controlling the erasing performance, which solves the problem that the time for a single erasing and pressing operation is fixed, and the erasing and pressing time required to complete the entire erasing operation will be longer, and even eventually cannot Problems completing wipe tasks

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