An instruction scheduling system and method for a reconfigurable array processor

An array processor and instruction scheduling technology, applied in instruction analysis, concurrent instruction execution, electrical digital data processing, etc., to achieve the effects of improving use efficiency, enhancing versatility, and improving compatibility
CN111897580BActive Publication Date: 2021-01-12BEIJING TSINGMICRO INTELLIGENT TECH CO LTD
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Patent Information

Authority / Receiving Office
CN · China
Patent Type
Patents(China)
Current Assignee / Owner
BEIJING TSINGMICRO INTELLIGENT TECH CO LTD
Publication Date
2021-01-12

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Abstract

The invention discloses an instruction scheduling system and method of a reconfigurable array processor, and belongs to the technical field of low-power speech keyword recognition. Includes: A data flow graph generated by a software algorithm. First check whether the data flow graph conforms to the hardware constraints of the reconfigurable array, use retiming technology to process the data flow graph, and then sort the instructions to be issued, and perform a hardware resource constraint check on the instructions issued at the same time, and the hardware resource constraint check passes Afterwards, the register resource constraint check will be performed on the data flow graph, and routing instructions will be inserted in the interval between instruction launches to ensure the correctness of the execution function. Finally, the maximum clique algorithm will be used to find the location of the processing unit corresponding to each instruction, and the instruction distribution will be completed. The invention solves the problem in the prior art that the final scheduling performance needs to be good only by relying on designers with solid hardware knowledge to design a good single-stage algorithm.
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Description

technical field

[0001] The invention belongs to the technical field of compilers based on special hardware architecture, and in particular relates to an instruction scheduling system and method of a reconfigurable array processor. Background technique

[0002] Reconfigurable arrays are a new general-purpose hardware design architecture at the forefront of academia. Usually a reconfigurable array is composed of some processing units with the same operation function. The computing functions that these processing units can implement are called operators. A computing unit contains multiple operators, and can perform different computing functions through different configuration instructions. The scheduling and issuing methods of configuration commands greatly affect the performance of reconfigurable arrays.

[0003] Existing scheduling algorithms divide instruction scheduling into multiple stages, including processing hardware architecture constraints, extracting data flow gra...

Claims

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