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Memory access interface device

An interface device, memory technology, applied in information storage, static memory, read-only memory, etc., can solve the problem of unable to achieve speed requirements, insufficient use, etc., to achieve the effect of phase adjustment

Active Publication Date: 2020-11-10
REALTEK SEMICON CORP
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

However, as the bandwidth requirements of products gradually increase, the traditional single data transfer rate mode architecture is no longer enough to meet the speed requirements

Method used

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Embodiment Construction

[0014] Please refer to figure 1 . figure 1 It is a block diagram of a memory 1 in an embodiment of the present invention. The memory 1 includes: a memory access controller 100 , a memory access interface device 110 and a memory device 120 .

[0015] The memory 1 can be electrically coupled with other modules through, for example, but not limited to, a system bus (not shown). For example, the memory 1 can be electrically coupled to a processor (not shown) through the system bus, so that the processor can access the memory 1 .

[0016] Among them, external access information, such as access information from the processor, can be received by the memory access controller 100 and sent to the memory access interface device 110, and then the memory access interface device 110 transmits the access information. The information is accessed in the memory device 120 .

[0017] In more detail, in one embodiment, the memory access controller 100 can receive and transmit access informati...

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Abstract

A memory access interface device that includes a clock generation circuit that generates reference clock signals according to a source clock signal and access signal transmission circuits are provided. Each of the access signal transmission circuits includes a first and a second clock frequency division circuits, a phase adjusting circuit and a duty cycle adjusting circuit. The first and the second clock frequency division circuits sequentially divide the frequency of one of the reference clock signals to generate a first and a second frequency divided clock signals respectively. The phase adjusting circuit adjusts the phase of an access signal according to the second frequency divided clock signal to generate a phase-adjusted access signal. The duty cycle adjusting circuit adjusts the duty cycle of the phase-adjusted access signal to be a half of the time period to generate an output access signal to access a memory device.

Description

technical field [0001] The invention relates to a memory access technology, and in particular to a memory access interface device. Background technique [0002] NAND flash memory early adopted a low-speed single data rate (SDR) mode architecture. However, as the bandwidth requirements of products gradually increase, the traditional single data transfer rate mode architecture is no longer enough to meet the speed requirements. Therefore, a non-volatile double data rate (NVDDR) mode architecture is proposed to break through the speed limit, and more and more high-speed specifications are proposed under this architecture. However, the controllers on the market are required to support all speed modes and have the capability of signal correction. [0003] Therefore, how to design a new memory access interface device to solve the above-mentioned deficiency is an urgent problem to be solved in the industry. Contents of the invention [0004] This Summary is intended to provide...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/12G06F13/16G06F1/06
CPCG06F1/06G06F13/124G06F13/1689G11C7/1066G11C7/1093G11C7/222G11C16/0483G11C16/08G11C16/32G06F1/08G06F1/12G11C8/18H03L7/07
Inventor 蔡福钦余俊锜张志伟周格至
Owner REALTEK SEMICON CORP
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