Reconfigurable array mapping method and device

Abstract

The invention relates to a reconfigurable array mapping method and device. The reconfigurable array mapping method comprises the following steps: acquiring a data dependence graph; and analyzing the data dependence graph to obtain the maximum time step TS _ max and the minimum starting interval; obtaining a reconfigurable computing architecture, and copying the first adjacent matrix and the secondadjacent matrix representing the reconfigurable computing architecture by the same number of layers as TS _ max to serve as a mapping space; under the integer linear programming model, respectively mapping the operation operation nodes, the intra-loop dependent edges and the inter-loop dependent edges in the loop structure to the mapping space.; and obtaining a mapping relationship between an operation node and an edge in the data dependence graph to the processing unit with the TS _ max layer expanded and the link. Modulo operation is conducted on the starting interval through the mapping relation to generate configuration information. According to the invention, a faster mapping speed, a higher resource utilization rate on CGRA and a smaller starting interval can be achieved.

Description

technical field [0001] The invention relates to the field of data processing, in particular to a reconfigurable array mapping method and device. Background technique [0002] Coarse-Grained Reconfigurable Architecture (CGRA), also known as reconfigurable computing architecture, has great application potential in accelerating computing-intensive applications. While CGRA retains hardware programmability, it also has performance close to that of an application-specific integrated circuit (ASIC). [0003] CGRA generally consists of multiple processing units (Processing Elements, referred to as PE), and the processing units perform functions similar to the arithmetic logic unit (ALU), such as addition and multiplication. In different CGRA architectures, PE functions may be different, and the interconnection modes between PEs may also be different. Users can configure PEs in CGRA to have different functions according to different computing requirements. [0004] In practical ap...

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Problems solved by technology

[0005] In the prior art, the vertex and edge in DDG are mapped to the hardware architecture of CGRA, and the generated hardware configuration has poor running performance on CGRA, such as a large startup interval (II) and low PE utilization

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