40 results about "Data dependency graph" patented technology

A method of allocating registers for a PAC processor. The PAC processor has a first cluster and a second cluster. Each cluster includes a first functional unit, a second functional unit, a first local register file connected to the first functional unit, a second local register file connected to the second register file, and a global register file having a ping-pong structure formed by a first register bank and a second register bank. After building a Component / Register Type Associated Data Dependency Graph (CRTA-DDG), a functional unit assignment, register file assignment, ping-pong register bank assignment, and cluster assignment of the invention are performed to take full advantage of the properties of a PAC processor.

A method, apparatus, and computer instructions for processing instructions. A data dependency graph is built. The data dependency graph is analyzed for recurrences, and unpipelined instructions that lie outside of the recurrences are expanded.

The invention discloses a method for reducing intraframe coding time delay in an HEVC encoder. The method includes the following steps: S1 making mode decision to a largest code unit to be coded to obtain the segmentation result of all of the sub-coding units and predicted mode decision results; S2 sending the results selected by the largest code unit to be coded to a scheduler; S3 generating a data dependence graph of the basic unit of the current largest code unit by the scheduler through a method of reverse triggering of labels; S4 driving an intraframe coding unit to perform operation based on the data dependence graph; and S5 preparing the data needed by a next intraframe coding unit by the scheduler based on the operation result and triggering the next intraframe coding unit to operate. The method reduces the time delay of a largest code module in an intraframe coding mode, the streamline processing can be carried out, and the problem that how to determine the dependency of the code units in high efficient video coding is solved by the method of reverse triggering of labels.

Provided is a modulo scheduling method. The modulo scheduling method includes conducting a search, based on a data dependency graph of a loop, for a recurrence in which a sum of iteration distances between command nodes is less than a predetermined critical value; and determining a processing order of the recurrence.

The invention discloses a cross-file inter-process optimization method based on an algebraic system. The method includes the following steps: according to the characteristics of the target machine, select instructions related to stack operations and logic operations, construct an algebraic system, and provide these instructions with the algebraic system. Establish a mapping relationship; traverse the program call graph PCG from the program entrance, and judge whether the nodes connected by edges belong to different source files, if so, continue to the next step, otherwise continue to traverse PCG; start from the function call instruction and follow The control flow graph CFG in the current function starts to traverse the data dependency graph DDG, generates the algebraic expression of the instruction stack operation, and performs expression reduction; analyzes the pop operation of the subsequent node function, reads the constant value from it, and passes it on in sequence , optimize and calculate, and finally delete redundant instruction fragments. The invention effectively merges and releases the optimizeable part in the function stack frame. In addition, the present invention also achieves better effects in cross-file process optimization, constant propagation and constant calculation.