The application discloses a
heuristic method suitable for instruction rearrangement of a multi-
transmitter processor, comprising the following steps: in a
data preparation stage, obtaining runtime parameters of each instruction according to
instruction set information and functional unit information, obtaining a
data dependency graph according to
data dependency relationships between instructions,
processing the
data dependency graph to obtain transmission priorities of the instructions, and then in a
simulation running stage, ensuring that the instruction transmission process meets constraint conditions of a parallel transmission instruction number, an available functional unit number and a pipeline function limit. The application also provides a device suitable for instruction rearrangement of the multi-
transmitter processor. The application solves the problem of instruction
parallel optimization caused by the performance decline of an application program due to the migration of
assembly codes between different generations of a domestic Shenwei many-core processor, improves the program
transplantation efficiency, and solves the adaptability problem of an application
assembly program
library to a dual-transmission pipeline
microstructure compared with the prior art.