Pointer synchronization device and method, asynchronous FIFO circuit and processor system

Abstract

The invention provides a pointer synchronization device and method, an asynchronous FIFO circuit and a processor system, the pointer synchronization device comprises a memory, a write index logic module and a read index logic module, the clock period of the write index logic module is a fast clock period, and the clock period of the read index logic module is a slow clock period; the write index logic module determines a write-in moment according to the fast clock period and the slow clock period and writes a first pointer into the memory at the write-in moment; the read index logic module reads the first pointer from the memory according to the slow clock period; wherein the writing moment meets the condition that the time difference of the same first pointer from being written into the memory to being read out from the memory is the first target delay time. The determination of the writing moment enables the time difference from writing to reading of the same first pointer to be thefirst target delay time which is shorter than the delay time in the prior art, so that the requirement of a high-performance processor for low delay of data transmission can be met.

Description

technical field [0001] The present application relates to the field of computers, and in particular, to a pointer synchronization device and method, an asynchronous FIFO circuit, and a processor system. Background technique [0002] When data is transmitted between different clock domains in a digital integrated circuit, it needs to be processed by a cross-clock domain circuit. Cross-clock domain circuits are usually asynchronous FIFO circuits. [0003] When an asynchronous FIFO circuit in the prior art performs cross-clock domain synchronization of pointers, it usually delays the clock cycle of the target clock domain by a delay of DFF number of clock cycles through a plurality of digital flip-flops (Digital Flip-Flops, DFF for short). Time, to achieve the synchronization of the pointer. [0004] In the prior art, the delay time when the pointers are synchronized across clock domains is relatively long, which cannot meet the low-latency requirements of high-performance pr...

AI Technical Summary

Problems solved by technology

[0005] The purpose of the embodiment of the present application is to provide a pointer synchronization device and method, an asynchronous FIFO circuit, and a processor system, so as to improve the problem of relatively long delay time in cross-clock domain synchronization of pointers in the prior art

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