Unlock instant, AI-driven research and patent intelligence for your innovation.

Full-unified PUF and TRNG hardware security primitive circuit based on FPGAs

A hardware security and circuit technology, applied in electrical components, impedance networks, multi-terminal networks, etc., can solve the problems of wasting entropy source circuits and differences in circuit effects, saving area overhead, reducing bit error rates, and solving statistical deviations. Effect

Active Publication Date: 2020-11-17
HEFEI UNIV OF TECH
View PDF4 Cites 0 Cited by
  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

In order to produce results, such PUF / TRNG needs to undergo separate design optimization and post-manufacturing calibration to produce better results. This behavior not only wastes a lot of entropy source circuits, but also makes the circuit effects vary with environmental changes. ; And the bigger problem is that if you use the PPMA protocol of the Internet of Things, you need to pay multiple times the overhead for device authentication

Method used

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
View more

Image

Smart Image Click on the blue labels to locate them in the text.
Viewing Examples
Smart Image
  • Full-unified PUF and TRNG hardware security primitive circuit based on FPGAs
  • Full-unified PUF and TRNG hardware security primitive circuit based on FPGAs
  • Full-unified PUF and TRNG hardware security primitive circuit based on FPGAs

Examples

Experimental program
Comparison scheme
Effect test

Embodiment Construction

[0040] In this embodiment, a fully unified physical unclonable function (Physical Unclonable Function, PUF) and true random number generator (True Random Number Generators, TRNG) hardware based on Field Programmable Gate Arrays (Field Programmable Gate Arrays, FPGAs) Safety primitive circuits such as figure 1 As shown, it includes: n rows and m columns of entropy source circuits, n data selectors, n entropy source collectors and deviation post-processing circuits; figure 1 The composition of the structure and the corresponding connections are given in .

[0041] Such as figure 2 As shown, any ith entropy source circuit is composed of a double-input NAND gate enabling signal unit and two single-input inverters, i∈[1,n×m];

[0042]The double-input NAND gate enable signal unit includes an enable input terminal EN, a data input terminal NAND and an output terminal NOUT;

[0043] Any single-input inverter includes an input terminal ROIN and an output terminal ROUT;

[0044] Th...

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

PUM

No PUM Login to View More

Abstract

The invention discloses a full-unified PUF and TRNG hardware security primitive circuit based on FPGAs. The circuit comprises an entropy source circuit, a data selector, an entropy source collector and a deviation post-processing circuit; the entropy source circuit is composed of a double-input NAND gate enable signal unit and two single-input inverters; and the deviation post-processing circuit comprises n first-order deviation post-processors, and any one first-order deviation post-processor comprises three D triggers, a two-input AND gate, an inverter and two exclusive-OR gates. According to the invention, the discarded entropy source can be collected in the PUF to provide dynamic entropy for the TRNG operation, so that two security primitives of TRNG and PUF can be designed at the sametime on one piece of Internet of Things edge equipment, the waste of an entropy source circuit is reduced and the robustness of the equipment is improved.

Description

technical field [0001] The invention belongs to the field of chip authentication and IP protection, in particular to a fully unified PUF and TRNG hardware safety primitive circuit based on FPGAs. Background technique [0002] With the deepening of the development of social information, information security issues are getting more and more attention. The key that is considered to be permanently stored and unknown to attackers is the core of traditional cryptography. However, many existing technologies can crack the traditional key, making the traditional key insufficient to guarantee the security of hardware. In order to effectively solve this security problem, PUF and TRNG came into being. PUF and TRNG are basic security primitives that support the basis of trust in a mutually authenticated public key infrastructure for digital signatures, certificate generation, and privacy protection. PUF uses the process deviation between chips during manufacturing to generate a sufficie...

Claims

the structure of the environmentally friendly knitted fabric provided by the present invention; figure 2 Flow chart of the yarn wrapping machine for environmentally friendly knitted fabrics and storage devices; image 3 Is the parameter map of the yarn covering machine
Login to View More

Application Information

Patent Timeline
no application Login to View More
IPC IPC(8): H03H7/38
CPCH03H7/38
Inventor 梁华国王燕捷王鑫宇鲁迎春蒋翠云易茂祥黄正峰
Owner HEFEI UNIV OF TECH