Register burst access control method, electronic equipment and storage medium

Abstract

The invention provides a register burst access control method, electronic equipment and a storage medium. The method comprises the steps of S1, receiving a read request and a write request sent by main equipment through multiple channels; S2, converting the currently received read request or write request through a sending interface protocol time sequence so as to send the read request and the write request to slave equipment through the same data sending channel; S3, converting response data fed back by the slave equipment corresponding to the read request or the write request by a receivinginterface protocol time sequence so as to feed back the response data of the slave equipment through the same data return channel, wherein the response data comprises read data information and read state information fed back corresponding to the read request, and write state information fed back corresponding to the write request; and S4, analyzing the receiving interface protocol time sequence, and feeding back the response data corresponding to the read request and the response data corresponding to the write request to the master device through different data return channels. According to the invention, the control logic is simplified, and data is transmitted in an assembly line mode.

Description

technical field [0001] The invention belongs to the field of integrated circuit design, and mainly relates to a method, a device and a storage medium for register burst access control. Background technique [0002] In the ASIC design, there are a large number of entries or registers on the slave device that can configure or record the running status of the chip; the master device (which can be an external or embedded master device, such as CPU, etc.) connected to the ASIC needs to read and write these entries. or register; this channel of reading and writing is called the register access interface. As the ASIC needs to support more and more functions and the logic design becomes more and more complex, more and more entries and registers need to be accessed by the master device. Access efficiency of table entries and registers is becoming more and more important. [0003] The main factors that affect the efficiency of the master device accessing these entries and registers ...

AI Technical Summary

Problems solved by technology

To forcibly use AXI to implement access logic, it will inevitably add too much conversion control logic, which is not worth the loss for the development of ASIC chips

In addition, in fact, the main application scenario of the AXI protocol is the interface design between the CPU and the cache (such as DDR or internal high-speed memory); the access to the table entries and registers of the slave device in the ASIC cannot be directly used

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