Methods to reduce the loading effect of different products in furnace tubes

Abstract

The invention discloses a method for reducing the load effect of different products in a furnace tube. , P is the graphic perimeter representing the unit area in a single shot, C is the graphic perimeter of a single chip, X is the number of rows of the chip in the shot; Y is the number of columns of the chip in the shot, and S is the Field shot size; Step 2 , define the perimeter of the graph per unit area in a single shot as the load effect value, and classify according to the load effect value; step 3, select the corresponding number of slices effect value according to the classification of the load effect value of the new product, Adjust the temperature of the five ends of the furnace tube, and use the light sheet to perform the off-line test operation of the film formation until the film thickness of the light sheet in the furnace tube reaches the test target film thickness; step 4, operate directly according to the category of the new product. The invention can quickly and accurately estimate the load effect of different products, can reduce the number of silicon wafers for trial operation of new products, and save trial operation time.

Description

technical field [0001] The invention relates to a semiconductor integrated circuit manufacturing technology, in particular to a method for reducing the load effect of different products in a furnace tube. Background technique [0002] With the development of integrated circuit technology and the continuous reduction of critical dimensions, thin film preparation technology has received more and more attention in semiconductor process manufacturing. In the production of semiconductor integrated circuits, the use of furnace tubes to grow thin films requires a long operation time, so generally in one batch (batch, that is, a collection of lots that have the same operating conditions at the batch operation equipment site and can work together at the same time) Multiple silicon wafer groups (lots, that is, a collection of silicon wafers with the same process flow) are placed in the same process for simultaneous operation, and these batches all use the same process conditions (reci...

AI Technical Summary

Problems solved by technology

[0009] 1. The perimeter of the step before film formation in the chip does not calculate the frame area (the remaining area after the die area is projected onto the shot area of ​​the silicon wafer), which has a great influence on the actual thickness;

[0010] 2. The height of the steps needs to be confirmed for the slicing results, and the trial run will take a long time;

[0011] 3. When the difference in load effect value between the two chips is less than 30%, arrange simultaneous operations. The difference of 30% is 1 / 6 of the load effect, and the thickness cannot be accurately controlled.

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