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Memory module

A technology of memory modules and memory chips, which is applied in the field of memory systems and can solve problems such as data loading capacity bottlenecks

Pending Publication Date: 2020-12-08
SAMSUNG ELECTRONICS CO LTD
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

For the computing power of information processing devices (such as servers) that handle big data, data loading capacity is a bottleneck

Method used

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Examples

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Embodiment Construction

[0025] figure 1 is a block diagram illustrating a memory system 100 according to example embodiments.

[0026] refer to figure 1 , memory system 100 may include non-volatile dual in-line memory modules (NVDIMMs) 110 and 120 coupled to host 105 . Host 105 can access NVDIMMs 110 and 120 . Host 105 may include a server, an array or farm of servers, a web server, a web server, an Internet server, a workstation, a minicomputer, a mainframe computer, a network appliance, a distributed computing system, a multiprocessor system, a processor-based system, or their The combination. Host 105 may include a processor (eg, a CPU core), processor cache, and a memory controller that controls NVDIMMs 110 and 120 . In this embodiment, two NVDIMMs 110 and 120 in memory system 100 are depicted. However, embodiments of the present disclosure are not limited thereto, and the memory system 100 may include various other numbers of memory modules.

[0027] Some examples may be described using th...

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Abstract

Provided are a non-volatile dual inline memory module (NVDIMM) supporting a DRAM cache mode and an operation method of the NVDIMM. The NVDIMM includes a DRAM chip, an NVM chip, and a controller that controls the DRAM chip to operate as a cache memory of the NVM chip. The controller sends a read command to the DRAM chip with reference to a cache address of data requested to be written from a host to the NVM chip, and sends a write command to the NVM chip with reference to an address of the data requested to be written at a time point when a read latency (RL) of the DRAM chip and a write latency(WL) of the NVM chip coincide with each other.

Description

[0001] Cross References to Related Applications [0002] This application claims U.S. Provisional Application No. 62 / 857,562 filed with the U.S. Patent Office on June 5, 2019 and Korean Patent No. 10-2019-0112369 filed with the Korean Intellectual Property Office on September 10, 2019 The disclosures of these applications are hereby incorporated by reference in their entirety. technical field [0003] Embodiments of the present disclosure relate to memory systems, and more particularly, to non-volatile dual in-line memory modules (non-volatile memory) for supporting dynamic random-access memory (DRAM) cache modes. volatile dual inline memory module, NVDIMM) and the operation method of the NVDIMM. Background technique [0004] In the field of information processing devices such as servers, there is an increasing demand for high-speed access to big data such as databases (DB) in the big data era. Data loading capacity is a bottleneck for computing power of information proces...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/0804
CPCG06F12/0804G06F13/1689G06F13/1673G06F12/0238G06F2212/205G06F12/0873G06F12/0831G06F12/0853
Inventor 林璇渶
Owner SAMSUNG ELECTRONICS CO LTD