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Chip power consumption optimization method, device, computer equipment and storage medium

An optimization method and power consumption technology, which is applied in computing, instruments, electrical digital data processing, etc., can solve problems such as insufficient power consumption reduction and unsatisfactory chip battery life, and achieve the effect of saving chip power consumption

Active Publication Date: 2021-09-24
CHINA SOUTHERN POWER GRID DIGITAL GRID RES INST CO LTD +2
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0004] The current multi-power domain technology is not enough to reduce power consumption when the chip is in some modes, and cannot meet the current people's needs for chip endurance

Method used

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  • Chip power consumption optimization method, device, computer equipment and storage medium
  • Chip power consumption optimization method, device, computer equipment and storage medium
  • Chip power consumption optimization method, device, computer equipment and storage medium

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Embodiment Construction

[0048] In order to make the purpose, technical solution and advantages of the present application clearer, the present application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain the present application, and are not intended to limit the present application.

[0049] The chip power consumption optimization method provided by this application can be applied to such as figure 1 shown in the chip power domain architecture. Among them, the whole chip system is divided into 5 power domains, which are power domain 1 (Always-on domain, normally open power domain), power domain 2 (Retention SRAM domain, static memory power domain), power domain 3 (CORE domain , core power domain), power domain 4 (BLE domain, Bluetooth power domain), power domain 5 (FLASH domain, flash memory power domain), each power domain uses its own voltage for pow...

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Abstract

The present application relates to a chip power consumption optimization method, device, computer equipment and storage medium. By adopting the present application, the automatic management process of chip power consumption optimization can be completed, and power consumption can be further saved. The method includes: by storing the wake-up mode command and the power-down mode command in the wake-up mode register and the power-down mode register respectively, in response to the above-mentioned power-down mode command, triggering the power-down enable register to start the power-down process, and Control the power domain specified by the above-mentioned power-down mode command to enter the low-power mode; receive the wake-up signal generated by the wake-up source corresponding to the above-mentioned wake-up source information; The power domain enters the power switching mode described above.

Description

technical field [0001] The present application relates to the technical field of batteries, in particular to a chip power optimization method, device, computer equipment and storage medium. Background technique [0002] With the development of the Internet of Things technology, people's demand for wearable electronic products has increased, and at the same time, there are further requirements for the battery life of wearable electronic products. However, due to the limitation of battery capacity development, the power consumption optimization of chips is becoming more and more be valued. [0003] There are many chip power optimization technologies, among which the multi-power domain technology is an effective and widely used technology. Multi-power domain technology divides the chip architecture into multiple power domains to supply power separately. Each power domain can use different voltages to supply power according to needs, and when a certain power domain is not requi...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F1/3234G06F1/3237G06F1/3287
CPCG06F1/3234G06F1/3237G06F1/3287
Inventor 李鹏李立浧于杨姚浩习伟匡晓云杨祎巍黄开天黄凯井铭蒋小文陈伟祥
Owner CHINA SOUTHERN POWER GRID DIGITAL GRID RES INST CO LTD
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