Multi-copy optimization method and system for read-only code segments of NUMA-aware SMP systems

Abstract

The invention discloses a multi-copy optimization method and system for read-only code segments of NUMA-aware SMP systems. The method comprises the following steps: configuring a local address and anapplication program local address for each SMP system; copying a kernel read-only code segment into the local addresses in each SMP system through SMC service; analyzing the read-only code segment parts of application programs in a binary or dynamic library loading process of the application programs, and copying the read-only code segment parts to the application program local addresses in each SMP system; and when each SMP system needs to execute a binary or dynamic library read-only code segment of a kernel and an application program, locally fetching an instruction directly through the local address or the local address of the application program. According to the method, the problem of far-end instruction fetching in the NUMA-aware SMP systems can be solved, software performance optimization is realized by utilizing an address localization technology, and better performance improvement can be obtained when network-on-chip and cross-path bandwidth are delayed and limited.

Description

technical field [0001] The invention relates to a server with a NUMA structure in the computer field, in particular to a NUMA-aware SMP system read-only code segment multi-copy optimization method and system. Background technique [0002] At present, the server is basically a multi-SMP system based on NUMA (non-uniform memory access) architecture. Under the NUMA architecture, each SMP system can be understood as a node (node), and the system composed of multiple SMP systems constitutes what we usually call "socket". . The socket's internal CPU access to remote node bandwidth and delay performance indicators are often better than the performance of local nodes. For multi-routing nodes, each node has its own CPU, memory and / or IO, and multiple sockets pass through Interconnect buses are linked together to form larger systems. However, due to the slow development of the interconnection bus, it cannot match the development of the CPU's exponential Moore's Law. Therefore, once ...

AI Technical Summary

Problems solved by technology

The root cause is that the multi-way server OS adopts a single image for the code segment, and the NUMA architecture adopted by the multi-way server will cause asymmetry in the delay and bandwidth of CPU access to local memory and remote memory.

Under the premise that the performance of the interconnection bus, especially the inter-circuit interconnection bus, is limited, there will be a large delay in remote instruction fetching, and this delay is related to the blocking state of the network-on-chip (NOC) link, so to a certain extent brings uncertainty to fetch

In addition, as the number of channels or cores increases, fragmented instruction fetching will also affect the available bandwidth of the on-chip network and interconnection bus.

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