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Storage unit based on four-transistor storage, storage array and in-memory computing device

Active Publication Date: 2020-12-29
中科南京智能技术研究院
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The six-tube structure has a larger area and greater power consumption

Method used

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  • Storage unit based on four-transistor storage, storage array and in-memory computing device
  • Storage unit based on four-transistor storage, storage array and in-memory computing device
  • Storage unit based on four-transistor storage, storage array and in-memory computing device

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Embodiment Construction

[0028] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0029] The object of the present invention is to provide a storage unit, a storage array and an in-memory computing device based on 4-tube storage, which improves the calculation accuracy.

[0030] In order to make the above objects, features and advantages of the present invention more comprehensible, the present invention will be further described in detail below in conjunction with the accompanying drawings and specific embodiments.

[0031] figure 1 It is...

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Abstract

The invention relates to a storage unit based on four-transistor storage. The storage unit comprises a first storage subunit, a second storage subunit, a bit line BL, a bit line BLB, a word line WL, aword line MWL, a word line MWLB, a bit line MBL, a first capacitor and a second capacitor. Each of the first storage subunit and the second storage subunit comprises a tube T1, a tube T2, a tube T3,a tube T4, a tube T5 and a tube T6; the first storage subunit and the second storage subunit have the same structure; the capacitor connecting end of the first storage subunit is connected with the first end of the first capacitor, the capacitor connecting end of the second storage subunit is connected with the first end of the second capacitor, and the second end of the first capacitor and the second end of the second capacitor are both connected with the bit line MBL. The capacity of the first capacitor and the capacity of the second capacitor are different. The method improves the calculation precision.

Description

technical field [0001] The invention relates to the technical field of in-memory computing, in particular to a storage unit based on 4-pipe storage, a storage array and an in-memory computing device. Background technique [0002] Deep convolutional neural networks (DCNNs) continue to demonstrate improvements in inference accuracy, and deep learning is moving to edge computing. This development has spurred work on low-resource machine learning algorithms and hardware to accelerate them. The most common operation in DCNNs is multiply and accumulate (MAC), which controls power and latency. MAC operations have high regularity and parallelism, so they are very suitable for hardware acceleration. However, the amount of memory access severely limits the energy efficiency of conventional digital accelerators. Therefore, in-memory computing (IMC) is increasingly attractive for DCNN acceleration. [0003] The current storage and calculation arrays are basically based on six or mor...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G11C11/418G11C11/412G06F7/544G06N3/063
CPCG06F7/5443G06N3/063G11C11/412G11C11/418
Inventor 乔树山黄茂森尚德龙周玉梅
Owner 中科南京智能技术研究院