High-speed peripheral system and control method thereof

Abstract

The invention discloses a high-speed peripheral system and a control method thereof, the high-speed peripheral system comprises a first chip and a second chip, and the first chip is connected with thesecond chip, wherein the first chip comprises a first emitter, a first receiver, a clock generator, a clock regulator, at least one emission buffer unit, at least one emission delay regulator, at least one reception buffer unit and at least one reception delay regulator; the second chip comprises a second receiver and a second emitter. According to the high-speed peripheral system and the controlmethod thereof provided by the invention, the delay measurement precision can be improved on the premise of low cost.

Description

technical field [0001] The invention belongs to the technical field of microelectronics and relates to a peripheral system, in particular to a high-speed peripheral system and a control method thereof. Background technique [0002] With the continuous evolution of semiconductors, many semiconductor components are developing toward specialized division of labor; for example, common memory, storage and other chips on the market are usually separated from the main chip, and finally use peripheral interfaces to connect the chips together. At the same time, with the rapid development of consumer electronics products in recent years, in order to improve the user experience, more and more software application functions are required, and the calculation delay is also required to be shorter and shorter. Therefore, the main chip uses the peripheral interface to transmit data among the chips. bandwidth requirements are getting higher and higher. [0003] The common way is to increase ...

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Problems solved by technology

Figure 4 It is a schematic diagram of the main chip writing to the sub-chip through multiple pins at high speed. The signal seen on the sub-chip, because the delay of each pin and the wiring is not completely aligned, the sub-chip cannot receive it correctly at the same clock. every bit of data

[0009] (2) Receive delay drift

Generally, the sub-chip manual only defines the maximum delay inside the chip, but there is no good way to measure the real delay of the actual sub-chip, and the receiving delay on the pin will drift with the process, and the working environment temperature is high or low. , voltage level, clock speed, and change; because the cycle of high-speed peripherals is very short, once the delay drifts, it will make it impossible for the main chip to get the data at the designed time point

For example Figure 5 Originally, the main chip was designed to read the data returned by the secondary chip at 2T, but in fact, after the receiving delay drifts backward, it needs to wait until 2.5T to read the data correctly

[0010] (3) Transmission delay drift

Figure 6 It is a schematic diagram of a peripheral interface. The main chip is designed to send instructions at clock 0T, while the sub-chip fetches instructions at 0.5T, and fetches data at 1.5 and 2.5T. However, the real sub-chip sees that the signal is routed through the pins. The delay drifts back and forth at the intersection of 0.5T, and every time the secondary chip fetches data at 0.5T, 1.5T, and 2.5T, it will fetch data that is being converted unstable and an error will occur

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