Programmable logic device grouping method and device

Abstract

The invention provides a programmable logic device grouping method and device, belongs to the field of integrated circuit chip design, and particularly comprises the steps of obtaining a physical circuit connection relationship between programmable logic devices and a logic circuit diagram; clustering logic circuit instances in the logic circuit diagram to obtain a plurality of subsets; distributing all the subsets to a programmable logic device according to a physical circuit connection relationship; optimizing and adjusting the subset allocated to the programmable logic device to obtain a theoretical set allocation scheme and an illegal connection list; constructing a multi-level jump point path for each logic circuit instance in the violation connection list; and modifying the logic circuit connection relationship according to the multi-stage jump point path, and outputting an actual design file corresponding to the physical circuit connection relationship. By means of the processing scheme, the programmable logic device grouping result which is minimum in segmentation interconnection, higher in speed and larger in data processing scale is obtained, and therefore the chip processing efficiency is improved.

Description

technical field [0001] The invention relates to the field of integrated circuit chip design, in particular to a programmable logic device grouping method and device. Background technique [0002] EDA technology is based on large-scale programmable devices, using computers as tools, completing expressions according to the hardware description language HDL, and realizing the goals of logic compilation, simplification, segmentation, layout, and optimization. With the help of EDA technology, the operator The description of hardware functions can be realized by using software, and the final design result can be obtained through FPGA / CPLD. Existing very large scale integration (VLSI: Very Large Scale Integration) refers to an integrated circuit with tens of thousands to millions of transistors integrated on a silicon chip of a few millimeters square, and a line width of less than 1 micron. Therefore, the complexity of VLSI circuits is a challenge for EDA design. Circuit segmenta...

AI Technical Summary

Problems solved by technology

Under this constraint, it is easy to divide the program blocks connected by multiple virtual circuits in the logic circuit design, and divide them into FPGAs without physical circuit connections, which will lead to the failure of the circuit design. Such logic circuit design division is Invalid segmentation, cannot be used in industrial design

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