Circuit for adjusting duty ratio of clock signal

Abstract

The invention discloses a circuit for adjusting the duty ratio of a clock signal, and relates to the field of integrated circuits. The circuit for adjusting the duty ratio of the clock signal comprises a first inverter module, a second inverter module, a first control tube, a second control tube, a first current mirror module and a second current mirror module, the first inverter module receives aclock signal input by a signal input end and sends the clock signal to the second inverter; the second phase inverter and the second control tube are connected to a signal output end, and a clock signal input by a signal input end is input to the second control tube after being reversed by the first phase inverter and the second phase inverter so as to control the on or off of the second controltube, so that the current flowing through the first control tube is increased or decreased, and therefore, circuit feedback is formed. According to the technical scheme, the current mirror module is used for mirroring the current source to the branch where the second control tube is located, and the duty ratio of the output signal is controlled by adjusting the magnitude of the mirroring current.

Description

technical field [0001] The invention relates to the technical field of integrated circuits, in particular to a circuit for adjusting the duty ratio of a clock signal. Background technique [0002] In modern circuit systems, the clock signal is the most commonly used signal, which can be generated by a crystal oscillator or an RC oscillator. Different circuit modules have different requirements on the clock signal. For example, the analog-to-digital converter requires the edge jitter of the input clock signal to be particularly small, the real-time clock circuit (RTC) requires the frequency of the input clock signal to be very stable, and the mixer (Mixer) in some radio frequency circuits requires a local oscillator The generated clock signal has a non-50% duty cycle to achieve the purpose of increasing the conversion gain, and the frequency doubling circuit requires the clock signal duty cycle to be 50%. However, in the prior art, the quality of the clock signal generated ...

AI Technical Summary

Problems solved by technology

However, the quality of the clock signal generated by the crystal oscillator or RC oscillator in the prior art is poor, and cannot meet the duty cycle requirements of the radio frequency circuit.

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