Integrated circuit layout method

Abstract

The invention discloses an integrated circuit layout method, which can reduce the potential drop of the result of an integrated circuit layout process, and comprises the following steps of: executingthe integrated circuit layout process to obtain an original integrated circuit layout; performing a potential analysis on the original integrated circuit layout to obtain a potential drop hot zone; determining a circuit density limit of the potential drop hot zone; and re-executing the integrated circuit layout process according to the circuit density limit to obtain an updated integrated circuitlayout.

Description

technical field [0001] The present invention is a method of circuit layout, and more particularly relates to a method of layout of an integrated circuit. Background technique [0002] In the design process of integrated circuits (such as application-specific integrated circuits (ASICs)), engineers will perform potential drop (IR drop) verification on circuits after timing closure (timing closure) before chip tape-out, in order to To ensure the stability of the circuit performance or the internal circuit of the chip will not be overheated. Due to the layout of certain components (for example: standard cells with large volume, strong thrust and concentrated distribution, or standard cells with small thrust driven by specific signal patterns), the potential drop problem is likely to occur, Manually adjusting the positions of these components or reducing the size (size-down) in the circuit after timing convergence is to solve the above problems by dispersing and reducing the lo...

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Problems solved by technology

[0003] As mentioned above, manually moving the components in the circuit may cause problems in the originally converged timing and/or leakage power problems. The subsequent correction process will not only increase the circu

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