Neural network tensor processor

Abstract

The invention discloses a neural network tensor processor. The neural network tensor processor comprises a main controller, a reconstruction controller and a data flow calculation engine, the main controller is used for providing a control and state interface of the neural network tensor processor for an external control unit, and providing first configuration information and a first initial signal for the reconstruction controller, the reconstruction controller receives the first configuration information and the first starting signal, obtains a reconstruction instruction of an external memory after the first starting signal is valid, and analyzes the reconstruction instruction to generate second configuration information and a second starting signal, and the data flow calculation enginereceives the second configuration information and the second initial signal, performs function configuration according to the second configuration information, acquires data and parameters of the external memory to execute operation after the second initial signal is valid, and writes a calculation result into the external memory. The tensor processor provided by the invention is suitable for carrying out centralized calculation on a neural network algorithm, and has universality and expandability.

Description

technical field [0001] The invention relates to the technical field of artificial intelligence chips, in particular to a neural network tensor processor. Background technique [0002] Processor technology is one of the major manifestations of human technological progress. However, the abstract model of a processor is quite simple: (1) the processor is composed of memory, input / output interface, control unit, and computing unit; (2) the processor performs the following operations in a loop: "fetch instruction / data, execute instruction , Write data"; (3) The behavior of the processor is completely determined by instructions and data. No matter how complex the processor is, be it CPU, GPU or DSP, the above model applies to all. This processor abstract model is the famous "von Neumann structure", the core of which is to store the program used for control as data. This computing model based on the stored program has been used until now. However, the complexity of the device st...

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Problems solved by technology

[0006] 3) MISD (Multiple Instruction Single Data): Multiple instructions process one data, which is not commonly used at present

However, the granularity of the calculation graph level is too coarse, and there is not much correlation between the various types. A typical neural network calculation consists of Convolution, Pooling, BN, Scale, RELU, etc., and their behaviors vary greatly. If the processor is designed according to the granularity of the calculation graph operation, this means that special computing hardware needs to be designed for each calculation graph operation (or a few) (just like NVIDIA DLA, NVDLA is specialized for convolution, pooling and BN Different computing circuits are designed), the cost is huge, and it is not scalable

[0018] Since artificial intelligence computing tasks are data-intensive tasks, the instruction pipeline architecture of traditional processors will introduce too much instruction redundancy, which is not conducive to the improvement of computing efficiency

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