A network detection method and system

Abstract

The embodiment of the present application provides a network detection method and system, which belong to the technical field of electronic design automation, specifically including: the host computer assigns identification information to each system board, programmable logic array, and signal channel, and assigns the identification information to each system board, programmable logic array, and signal channel. Load the corresponding controller; set the signal channel to receive signal mode uniformly; detect whether the signal channel receives a data packet; generate an interconnection data, and the host computer obtains the interconnection information according to the interconnection data processing, and generates a description of the network connection Hardware system description language files. Through the processing scheme of the present application, manual measurement and input are not required, and the installation environment of the development board is not restricted, the generation speed is fast and the precision is high, and the faulty cable can be accurately located.

Description

technical field [0001] The present application relates to the technical field of electronic design automation, and in particular to a network detection method and system. Background technique [0002] With the development of the chip industry, the integration of chips is getting higher and higher, and the scale of logic gates is getting larger and larger, which also poses challenges to the verification of logic design. In the prototype verification based on programmable logic array (FPGA), often When FPGA resources cannot meet the needs, it is necessary to use multiple FPGAs and connect them through input / output (IO) port networking to form larger logic resources to meet design needs. Different logical designs have different topology requirements for networking. For example, some adopt star topology, some adopt matrix topology, and some adopt queue topology. Therefore, in the prior art, all the IO port resources of each FPGA are grouped according to a fixed number (commonly...

AI Technical Summary

Problems solved by technology

Although the operation of visual inspection is simple, the accuracy cannot be guaranteed

The multimeter has high detection accuracy, but manual measurement is required, and for the highly integrated connector with the bottom patch method, the pins are not all exposed outside, and the operation of the multimeter's needle to measure the signal is difficult.

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