Convolution operation acceleration method for carrying out weight splitting according to bit precision

A convolution operation and bit precision technology, applied in the field of convolution operation acceleration, can solve the problem of limited multiplication reduction, and achieve the effect of increasing the upper limit of parallelism, high algorithm parallelism, and reducing data access time

Active Publication Date: 2021-03-02
XI AN JIAOTONG UNIV
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  • Application Information

AI Technical Summary

Problems solved by technology

[0009] 3. CNN implements the functions of classification and recognition. When deploying CNN accelerators in applications such as automatic driving, peripheral circuits are still required to r...

Method used

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  • Convolution operation acceleration method for carrying out weight splitting according to bit precision
  • Convolution operation acceleration method for carrying out weight splitting according to bit precision
  • Convolution operation acceleration method for carrying out weight splitting according to bit precision

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Embodiment

[0096] Taking the 8-bit quantized 3×3 convolution kernel as an example, in this test, the hardware structure of MF-Conv can be specifically expressed as:

[0097] (A), 9 groups of comparator arrays, wherein each group is composed of 8 1-bit comparators;

[0098] (B), an accumulator array, is made up of 8 accumulators, wherein each accumulator is made up of 8 adders;

[0099] (C), pipeline register;

[0100] (D), accumulating summation logic block, is made of 7 adders;

[0101] According to the division method of the present invention, the critical path of the circuit is truncated by the pipeline register between the accumulator array and the accumulation and summation logic block, so that the circuit obtains a higher clock frequency, thereby improving the efficiency of convolution calculation. Compared with the existing convolution calculation acceleration method, the present invention completely avoids the multiplication calculation, and further improves the upper limit of ...

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Abstract

The invention discloses a convolution operation acceleration method for carrying out weight splitting according to bit precision, and the method comprises the following steps: 1), carrying out the traversal and comparison of each bit of each weight W in a convolution kernel, marking non-zero elements ck * k'and q in all bit data, marking input feature map data FIk * k 'corresponding to the weightWk * k' to which the position belongs, transmitting the marked input feature map data FIk * k 'to FIk * k' and q ', and supplementing the unmarked FIk * k' and q 'with' 0 '; 2) for each bit, accumulating all input data classified and given to the current bit; 3) multiplying the accumulation result under each q bit by 2q; 4) accumulating results obtained by shift calculation again to obtain outputfeature map data FO of the current convolution operation; and iteratively repeating the steps 1) to 4) to generate output feature map data of all convolution channels. According to the invention, theconvolution operation gets rid of the dependence on on-chip DSP resources, and the upper limit of the calculation parallelism degree that the convolution operation can reach is improved.

Description

technical field [0001] The invention relates to a convolution operation acceleration method for performing weight splitting according to bit precision. Background technique [0002] Convolutional neural network (CNN) has been widely used in image classification and speech recognition. CNN is built by imitating the biological visual perception mechanism. Visual perception is mainly composed of multi-layer neurons that process data. Mapped to the CNN network structure, it is embodied as a multi-layer convolutional layer connection. According to statistics, volume Product calculation accounts for 99% of the total computation of CNN. In recent years, many applications including autonomous driving have put forward higher real-time requirements for CNN. Therefore, the design of CNN accelerator has become the mainstream research direction in the industry. [0003] High flexibility, low cost, and short design cycle make FPGA-based CNN accelerator designs more suitable for deployme...

Claims

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Application Information

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IPC IPC(8): G06N3/063G06N3/04G06T1/20G06T1/60
CPCG06N3/063G06T1/20G06T1/60G06N3/045
Inventor 杨晨吕娴娴范世全耿莉
Owner XI AN JIAOTONG UNIV
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