24 results about "Bit blit" patented technology

An apparatus may receive T copies of data that includes a cyclic redundancy check (CRC). T is an even number greater than or equal to 4. The apparatus may determine a first set of bit positions, at each of which T / 2 copies of the data have a same first bit value different from a same second bit value of the other T / 2 copies of the data, determine a second set of bit positions, at each of which more than T / 2 copies of the data have a same bit value different from a bit value at a corresponding bit position of the first copy, and correct, using the first set of bit positions and the second set of bit positions, an error contained in the first copy.

The embodiment of the invention provides an ID allocation method and device and a storage medium, and the method comprises the steps: setting a layered cache architecture which comprises an L1-layer cache from bottom to top to an Ln-layer cache, the Ln-layer cache is provided with a bitmap of N bits, each bit maps an Ln-1-layer cache, and the bit value of the bit represents the resource state of the Ln-1-layer cache; n bits in the L1-layer cache map N IDs (Identity); offsets of all layers from the Ln-layer cache to the L2-layer cache are sequentially obtained, the available L1-layer cache is positioned according to the offsets of all the layers, the minimum bit with the bitmap being 0 in the available L1-layer cache is obtained, the minimum bit is an available ID identification bit, and the available ID identification bit is set to be 1 and used for marking that the ID is allocated; and determining an integer ID corresponding to the available ID identification bit according to the offset of each layer of cache. According to the method, the ID allocation performance is improved.

The invention provides a coding method, a decoding method and a display device, and the coding method comprises the steps: obtaining a first initial data stream, carrying out the operation of the first initial data stream according to a preset logic operation relation, outputting a target coding feature value obtained through the operation, judging whether the target coding feature value meets a first preset condition or not, and if yes, carrying out the decoding. Under the condition that the target coding characteristic value meets a first preset condition, assigning the bit number of the ith bit of the first initial data stream as the bit number of the (i + 1) th bit of a first target data stream to be output, and assigning a first target bit number obtained by carrying out logical NOT operation on the bit number of the first bits of the first initial data stream as the bit number of the first bits of the first target data stream, and outputting the first target data stream, so that the coded first target data stream with nine bits can be obtained through the logical NOT operation, and the coding efficiency of the first target data stream is improved. While the bandwidth utilization rate is improved, the logic operation complexity required by coding is also reduced.

The invention discloses a task scheduling method, electronic equipment, a storage medium and a computer program product. The method comprises the following steps: detecting an operation mode of a physical processor to obtain a detection result; in response to the detection result indicating that the physical processor is switched from the physical mode to the virtualization mode, a target scheduling priority to be scheduled is determined based on an operation bitmap in an operation queue structure corresponding to the physical processor, and different bits in the operation bitmap correspond to different scheduling priorities respectively; and scheduling the to-be-executed scheduling task in the target scheduling queue corresponding to the target scheduling priority. The technical problems of poor task scheduling timeliness, low accuracy and low system resource utilization rate are solved.

The invention discloses an electric energy meter data freezing method and an electric energy meter data freezing system for decentralized freezing based on a special data container. The method comprises the following steps of: copying data of all freezing data types required in the special data container from one type of cache to the special data container at the freezing moment; querying a freezing type demand at the current moment, and setting a corresponding bit in the bitmap according to the freezing type demand at the current moment; sequentially querying the bitmap according to bits in a set period, if the bits are set, extracting corresponding frozen data from the special data container according to the frozen data type required by the freezing type corresponding to the bits, writing the corresponding frozen data into the nonvolatile memory, and resetting the bits; after the Nth set period, stopping bitmap query, clearing the bitmap, and waiting for the next freezing moment; n is the number of defined freezing types, and the set period time * N is smaller than the minimum freezing period. According to the method, system jamming caused by writing a large amount of frozen data into the nonvolatile memory at the freezing moment can be avoided.

The invention relates to the technical field of computers, and discloses a graphical interface video memory optimization method and device, electronic equipment and a medium, and the method comprises the steps: obtaining color data of a target pixel, the color data being a first color value in a first color space; converting the first color value into a corresponding index value; determining a target storage unit and bit offset in the frame buffer according to the coordinate of the target pixel, and writing the index value into a specified bit starting from the bit offset in the target storage unit; in response to the display request, reading a corresponding index value from the frame buffer according to the coordinate of the target pixel; and converting the read index value into a second color value in the first color space, and displaying the second color value. According to the method and the device, stable display under video memory driving can be realized on the premise of not increasing hardware cost, the problem that video memory driving cannot be adopted due to overlarge occupation of the video memory is solved, and meanwhile, the problem that the display effect is relatively poor due to a direct driving mode is avoided.

The present disclosure provides a simulation data transmission method adapted to transmit data of a three-dimensional simulation space over a network for rendering presentation on at least one graphical user interface, the method comprising: performing a first calculation comprising processing particles of the three-dimensional simulation space according to a smoothed particle hydrodynamic algorithm, generating first particle data; executing first coding according to the first particle data to generate second particle data; executing compression according to the second particle data to generate third particle data; and transmitting the third particle data through the network. According to the method, the bit mark, the space division, the data compression and the sliding window are combined, the technical scheme for real-time data transmission between the SPH particle system and the graphic rendering system is formed, the method does not depend on network hardware or protocols, and the system complexity and the deployment cost are reduced.

The application provides a method and system for improving the diversity of bit-level autoregressive image generation, and relates to the technical fields of artificial intelligence and computer vision, and has the characteristics that in the sampling process of a bit-level autoregressive image generation model, for each generation scale k, the original prediction logits of all token bits at the scale are obtained; based on the original prediction logits, an adaptive temperature coefficient τk is dynamically solved by a binary search algorithm, so that after the logits are scaled by the τk and normalized by softmax, the difference between the actual average maximum bit probability of the current scale k and the preset target average maximum bit probability Sk is less than the preset tolerance; an adaptive temperature coefficient τk is dynamically determined by binary search, so that after the softmax normalization is applied to the τk. The application has the advantages that the generation diversity is improved by adaptively smoothing the early prediction distribution, and the visual quality is maintained by means of energy-based path search; the method mainly operates in the early stage with low computational overhead, and the inference delay is only slightly increased, and the core design can be extended to similar autoregressive generation models.

Disclosed in the present application are a data encoding method and chip, a data decoding method and chip, and a display apparatus. Second bit data is added after first bit data in first image sub-data so as to obtain second image sub-data; address information and numerical information of a first piece of consecutive bit data in the second image sub-data are written into predetermined bits of row configuration information of the second image sub-data; and address information and numerical information of an (N+1)th piece of consecutive bit data in the second image sub-data are written into bits where an N-th piece of consecutive bit data in the second image sub-data is located, thereby reducing extra overheads.

The invention provides a method and device for improving data storage, a storage control chip and a storage medium. The method comprises the following steps: executing full-disk reading and writing of Flash to obtain a bit of each Page in each Block; according to the bit of each Page in each Block, judging whether each bit column in each Block is good or bad by adopting a preset judgment rule, and generating an exclusive bad list of each Block; and storing the exclusive bad list of each Block. By generating and storing the exclusive bad list of each Block, data reading and writing can be achieved according to the exclusive bad list of each Block when Flash reading and writing operation is executed, and compared with a mode of adapting to a public bad list, the risk that more error bits happen to data is well reduced, and the data reading and writing stability of Flash can be improved.

The application provides a data storage method and device, electronic equipment and storage medium, and relates to the technical field of computers. The method comprises the following steps: acquiring signaling data of a user; constructing a bit slice index (BSI) of a bit map based on the signaling data; and constructing a compact matrix corresponding to the bit slice index. The columns in the compact matrix do not contain all-zero columns. The all-zero column can be understood as no signaling data at this moment, so the all-zero column in the bit slice index is removed and converted into the compact matrix, which can save storage resources. In addition, the bitmap formed by the compact matrix is compressed and stored according to a Roaring Bitmap data structure. Since the Roaring Bitmap data structure can efficiently compress data, the storage resources can be further saved, and the occupation of the signaling data storage resources can be effectively reduced.

The invention belongs to the technical field of database systems, and particularly discloses a bitmap multi-version processing method and device based on hierarchical grouping difference, and the method comprises the steps: obtaining a bitmap modification record from a bitmap version log recording module; a bitmap modification record is processed through a hierarchical grouping differential bitmap storage module; wherein the hierarchical grouping differential bitmap storage module is used for storing one or more version groups; the version group is configured with a reference bitmap and a differential bitmap; the differential bitmap is based on the reference bitmap, and the bit position, changed relative to the reference bitmap, in the corresponding bitmap version is recorded; the hierarchical grouping differential bitmap storage module is used for judging whether a new version group is established or not based on the group capacity; and if so, creating a new version group based on the bitmap modification record, and if not, creating a new differential bitmap based on the bitmap modification record, and inserting the new differential bitmap into the recently created version group. According to the method and the device, the memory occupation amount of the bitmap version can be effectively reduced.

The technical concept of decomposing data according to bit width provided by the embodiments of the present specification is that the bit width decomposition instruction is decomposed into a plurality of decomposition processes of decomposition periods through a shift operation, the number of decomposition periods is determined by the bit width to be decomposed and the target bit width, the lowest bit of the remaining bits to be decomposed of the bits to be decomposed is aligned with the lowest bit of the storage unit, and the target value is obtained by combining the bitwise AND operation with the mask word. The technical scheme is beneficial to fully utilize the hardware storage resources and improve the processing efficiency.

The present application discloses a data encoding method and chip, a data decoding method and chip, and a display device. The data encoding method comprises: acquiring image data for input to a display panel, wherein the image data comprises a plurality of pieces of sub-image data, and each piece of sub-image data comprises a plurality of data combinations; acquiring addresses of specific data in each data combination of each piece of sub-image data, wherein the specific data has M bits, and the bit values of the M bits are all 0 or 1, M being an integer greater than or equal to 2; writing the address and bit value of the first piece of specific data in the data combination to a preset bit combination among a plurality of preset bit combinations of line configuration information of the sub-image data; and writing the address and bit value of the (N+1)-th piece of specific data in the data combination to a bit where the N-th piece of specific data in the data combination is located.

The application discloses a sparse convolution accelerator based on a mixed bit width, which comprises a total control module, a DMA, a first calculation core and a cache module.The total control module is used for controlling the overall operation of the sparse convolution accelerator based on the mixed bit width; the DMA is used for carrying out the carrying of image data and weights in and out of a chip; the first calculation core is used for completing the acceleration of the sparse convolution layer of the mixed bit width; and the cache module is used for caching and multiplexing data.The application proposes a CNN multiplication accumulator structure which takes a low-bit-width multiplier as a basic unit, supports mixed precision calculation through addition, shifting and flexible combination of the basic unit, and flexibly and efficiently realizes the hardware acceleration of convolution operators of different compression network models.The application can be widely applied to the field of chip design.

The application provides a data processing method, system and related equipment, which can be applied to the field of computer technology. The method comprises the following steps: acquiring a first group of data comprising first data and second data, and outputting a second group of data comprising third data and fourth data. The first data and the second data each occupy a first number of bit positions, the third data and the fourth data are data obtained by compressing the first data and the second data respectively, the third data occupies a second number of bit positions, the fourth data occupies a fourth number of bit positions, the sum of the second number and the third number is less than or equal to the first number, the sum of the fourth number and the third number is less than or equal to the first number, and the third number is the number of bit positions occupied by the sign bit and the index bit of the floating-point type data. Therefore, the method can make the number of bit positions occupied by the compressed data much smaller than the number of bit positions occupied by the data before compression, reduce the compression rate of the data, and thus reduce the data storage cost of the database.

The invention relates to the technical field of solid-state storage, in particular to a flash original data analysis method and device and a medium. According to the method, when a read command error correction failure occurs, a data analysis command is sent out, 0 / 1 bit number statistics is carried out on an effective part in an original data block, and then randomized seed combinations are extracted; and under the condition that the randomized seed combination is effective, performing software descrambling operation on the user data and the metadata by using the randomized seed combination, restoring the scrambled data into a data plaintext, and comparing the data plaintext with the reference standard data, recording the offset position of the difference byte, the bit error mode and the total number of bit flipping, and outputting to an analysis log; and if not, recording the data plaintext and the randomized seed initial value to the analysis log, and outputting the analysis log. According to the method, original data is descrambled and decoded through software, and user data and metadata are restored into plaintexts, so that comparison with standard data is facilitated.

The application provides a method for remote injection of a system under U-Boot in a space environment, and belongs to the field of data processing. The method comprises the following steps: in a booting stage, determining an update mode and a switching entry; initializing a buffer area and establishing a receiving state bitmap; analyzing a TTE network protocol frame; performing fixed identification verification and single data segment integrity verification, writing data segments into corresponding offset positions of the buffer area, and setting corresponding bit positions in the receiving state bitmap; extracting total data segment information, feeding back a data segment serial number corresponding to an unset bit position as a missing segment serial number, and performing a closed loop for retransmission; when all valid bit positions determined by the total data segment number are set, performing overall consistency verification and setting a safety gate; and performing image writing. The application solves the problems of complex links, insufficient real-time performance, lack of update capability in the booting stage, insufficient data transmission certainty and reliability, redundant processing paths, and high system complexity.

This application discloses a data repair method and related apparatus, applicable to high-performance computing and other scenarios, to promptly repair faulty bits and ensure the correctness of subsequent HBM data reading and writing. The method includes: obtaining first information including a first field, the first information indicating the repair operation identified by the first field to be performed on the faulty byte in the faulty Dword that needs to be repaired; after determining that the repair operation identified by the first field needs to be performed on the faulty byte in the faulty Dword according to the first information, obtaining the first bit of the faulty byte, the first bit being the faulty bit in the Dword; obtaining the bit width value of the second bit of the target byte, the target byte being either the faulty byte or a redundant byte in the HBM; updating the bit width value of the first bit of the faulty byte based on the bit width value of the second bit of the target byte to repair the first bit.

The invention discloses an adaptive variational mode noise reduction method and system based on bit plane decomposition, and belongs to the field of signal processing. According to the technology, binary conversion is carried out on a time domain signal through an innovative bit plane decomposition method, the signal is decomposed into time domain components under different bit resolutions, and the optimal decomposition parameter of VMD is adaptively determined based on component characteristics. The method comprises the following steps: firstly, carrying out bit plane decomposition on a noisy signal to obtain time domain components of different bits; calculating an autocorrelation test value of each component, and distinguishing a signal component and a noise component; dynamically calculating the modal number and penalty factor of the VMD according to the number of signal components and the energy entropy; and finally, performing VMD decomposition and reconstructing a noise reduction signal. Transient features are reserved through bit plane decomposition, and the feature retention rate is remarkably improved; vMD parameters are directly calculated, iterative optimization is avoided, and the processing speed is greatly increased; hardware resource occupation is greatly reduced, and power consumption is greatly reduced; and in a strong noise environment, the accuracy is greatly improved.

This application discloses a method, apparatus, medium, and device for simulating single-event upset effects in graphics processing units (GPUs), relating to the field of aerospace computing hardware reliability testing technology. The method includes: measuring the access latency difference between virtual addresses based on a virtual address range; determining, based on the access latency difference, virtual addresses physically located in the same row within the GPU, as well as virtual addresses located in the same memory bank but not in the same row; inputting device parameters and orbital parameters into a preset hammer-iteration number prediction model for prediction, obtaining the corresponding hammer-iteration number for the GPU; performing hammer-iteration tests based on the hammer-iteration number, and the virtual addresses in the same row and those in the same memory bank but not in the same row, obtaining the bit flip rate of the GPU under conditions of protection measures being enabled and disabled; and evaluating the error correction capability level of the protection system based on the bit flip rate. This application is adaptable to the special architecture of GPUs.

The application provides a data bit width conversion method, system, device, storage medium and program product. Image data of a first bit is received. Parameters of a bit adjustment model are adjusted according to the image data of the first bit and preset bits. Then, the image data of the first bit is converted and output as image data of the preset bits according to the bit adjustment model. The image data of the preset bits is used as input data for neural network processing, so that the image data of the preset bits can be provided for neural network processing, the demand of neural network processing is met, the correctness of data processing is improved, and the data storage space and the bandwidth of transmission are reduced.

The invention discloses a graphic processor single event upset effect simulation method and device, a medium and equipment, and relates to the technical field of aerospace computing hardware reliability testing. The method comprises the following steps: based on a virtual address range, measuring an access delay difference between virtual addresses; based on the access delay difference, virtual addresses physically located in the same row in the graphics processor and virtual addresses located in the same memory bank but in different rows are determined; inputting the device parameters and the orbit parameters into a preset hammering iteration number prediction model for prediction, and obtaining the hammering iteration number corresponding to the graphics processor; based on the number of hammering iterations, the virtual addresses in the same row and the virtual addresses in the same memory bank but in different rows, performing a hammering test to respectively obtain the bit flipping rates of the graphics processor under the conditions that the protective measures are started and not started; and based on the bit flipping rate, evaluating an error correction capability level of the protection system. The method can adapt to the special architecture of the GPU.

The application provides a bitmap processing method and device, the method comprising: receiving a first operation instruction input by a user, the first operation instruction comprising an index to be viewed, the index to be viewed being convertible into a string having N bits; if a type of a SuperBlock is a first type, selecting a first bit corresponding to a semi-full submap PartiaMap included in the SuperBlock according to a first number of high bits included in the string; if the first bit corresponding to the semi-full submap is set, obtaining a number of bits set below the first bit from the semi-full submap; determining a position of the number in a semi-full array included in a management block according to the number, and determining a second bit in a first Block corresponding to the string according to the position; and displaying an operation result to the user, the operation result comprising a current state of the second bit.