Mask operation method of explicit independent mask register in GPU

Abstract

The invention belongs to the technical field of image processing units, and particularly relates to a mask operation method of an explicit independent mask register in a GPU (Graphics Processing Unit), which comprises the following steps: S1, each GPU hardware thread can access respective eight 128-bit wide independent mask registers, and the eight 128-bit wide independent mask registers are recorded as m0-m7; according to the mask operation instruction of the explicit independent mask register in the GPU, each hardware thread in the GPU can access respective eight 128-bit wide independent mask registers, and four groups of mask operation instruction users can use the mask operation instruction to realize reduction operation, extension operation, logic operation and data movement among universal vector registers of the mask register respectively; the instruction can realize the generation of a branch mask in condition control, and meanwhile, the mask value is solved, so that the instruction transmitting process in the programmable core is optimized, invalid operand reading and pipeline operation execution are avoided, and the programmable power consumption is reduced.

Description

technical field [0001] The invention relates to the technical field of image processing units, in particular to a mask operation method of an explicit independent mask register in a GPU. Background technique [0002] Modern graphics processors contain many programmable processor cores and graphics-specific hardware acceleration units for executing shader codes. Initially, these processor cores were used to execute shader codes in graphics applications, and later found that they can handle non-graphics calculation-intensive tasks very well. applications, developed into a general-purpose graphics processor. [0003] In graphics applications, the GPU has to process a huge number of vertices and fragments. It is impossible to write codes for each of these objects individually. Therefore, the GPU programming model defines shaders for processing vertices and shaders for processing fragments. Users can The algorithm for processing vertices and fragments is described in Shader. A s...

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Problems solved by technology

[0005] The purpose of the present invention is to provide a mask operation method of an explicit independent mask register in the GPU, to solve the problem that the graphics processor proposed in the above-mentioned background technology combines multiple vertices or work items in the kernel into threads, according to single instruction multiple Data mode to execute the corresponding shader program and kernel program. When conditional control codes appear in the program, one method of SIMD implementation to solve this problem is to use the execution mask to control the output of the execution result. Only when the corresponding bit in the mask When the value is 0x1, the corresponding destination operand will be rewritten. In order to save the encoding space of the GPU instruction word, a single implicit mask register is often used in graphics processors. When the conditional control statement in the shader or kernel code is relatively When multiple or nested, using a single implicit mask register ($exec) cannot change the mask register of the current instruction, resulting in frequent movement of data between the implicit mask register and general-purpose registers. In this way, not only additional Increase the number of program instructions, increase the execution delay of the program, and at the same time, the additional reading and writing between registers will increase the power consumption of the programmable processor core

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