Clock data recovery circuit, method and device

Abstract

The invention discloses a clock data recovery circuit, method and device. The circuit comprises a receiving module used for receiving analog signals; the first equalization module is connected with the receiving module and comprises a first totalizer and a second totalizer; the first sampling module is connected with the output end of the first totalizer and comprises a first edge sampler and a second edge sampler which are respectively connected with the output end of the first totalizer; the second sampling module is connected with the output end of the second totalizer; the data processingmodule is connected with the first sampling module and the second sampling module; the clock recovery module is connected with the data processing module; and the output module is connected with the clock recovery module. Through the mode, the phase can be adjusted by adopting the bias voltage, so that the clock information can be accurately recovered.

Description

technical field [0001] The invention relates to the technical field of electronic circuits, in particular to a clock data recovery circuit, method and device. Background technique [0002] Clock and data recovery (CDR) circuits are important receiver (RX) components in serializer / deserializer (SerDes) designs, such as high-speed serial input / output (I / O) designs. In order to transmit serial data at high speed, the CDR extracts phase information from received serial data and generates a clock synchronized with the data, outputs recovered clock and data signals for the RX part. [0003] Whether the phase of the recovered clock is at the optimal phase (that is, the maximum eye width and eye height) is an important indicator of the quality of CDR. The phase detection is composed of a phase detector. The difference between different CDR schemes lies in the phase detector. In the case of no decision feedback equalizer (DFE) equalization, the existing scheme has a simple structure...

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Problems solved by technology

In the case of no decision feedback equalizer (DFE) equalization, the existing scheme has a simple structure, but the phase cannot be fine-tuned when the phase is not at the optimal position; in the case of DFE equalization, the phase is completely controlled by the phase detector, and the phase not necessarily in the best position

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