Electrostatic discharge protection clamping circuit of silicon-on-insulator circuit

Abstract

The invention belongs to the technical field of semiconductors, and discloses an electrostatic discharge protection clamping circuit for a silicon-on-insulator circuit, which is used for a circuit which requires that a discharge path cannot exist between a control port and a power supply and between a data port and the power supply, and that the power supply and an OUT port only allow two or moreMOS transistors to be connected in series. The circuit comprises a port PAD, a first electrostatic impedor, a second electrostatic impedor, a third electrostatic impedor, a fourth electrostatic impedor, a fifth electrostatic impedor and a sixth electrostatic impedor and a pseudo power supply; the port PAD is also connected with a pseudo power supply through a first electrostatic impedor and a fifth electrostatic impedor in sequence; the port PAD is grounded through the second electrostatic impedor; the port PAD is also grounded through a third electrostatic impedor; the port PAD is also grounded through a sixth electrostatic impedor and a fourth electrostatic impedor which are sequentially connected in series; the port PAD is also grounded through a first electrostatic impedor and a thirdelectrostatic impedor which are sequentially connected in series; and a protection object connecting port is connected between the sixth electrostatic impedor and the fourth electrostatic impedor. According to the electrostatic discharge protection clamping circuit provided by the invention, the electrostatic discharge protection performance of the circuit is improved on the premise of meeting thecold backup characteristic requirement of the circuit.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to an electrostatic discharge protection clamping circuit for a silicon-on-insulator circuit. Background technique [0002] With the development of the semiconductor industry, especially after entering the deep submicron scale, due to the characteristics of thin silicon film and poor heat dissipation ability of SOI technology, the electrostatic discharge (ESD) protection ability of the drain end of the output tube becomes very poor. In the SOI process, the industry usually adopts the ESD global protection structure to solve the problem of poor ESD current discharge capability at the output terminal / bidirectional terminal of the SOI chip and the limited discharge capacity of the single loop bleeder tube, which makes the ESD protection of SOI integrated circuits Ability has been comprehensively improved. However, for some SOI circuits with special requirements, such as Figure...

AI Technical Summary

Problems solved by technology

[0003] The present invention provides a silicon-on-insulator circuit electrostatic discharge protection clamping circuit, aiming at the requirement that neither the control port nor the data port have a discharge path between the power supply and the power supply and OUT The port only allows two or more MOS transistors to be connected in series, and there is no port circuit equipped with its own pseudo power supply in the circuit, so as to improve the ESD protection ability of such special-demand circuits

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