Digital signal time delay method based on FPGA and high-precision time delay chip

Abstract

The invention discloses a digital signal delay method based on an FPGA (Field Programmable Gate Array) and a high-precision delay chip. The method comprises the following steps: firstly, calculating adelay parameter of a front edge or a rear edge of a digital signal by utilizing a delay duration T set by a user, a width Tw of a delayed output pulse and a measured time value T1 of an input signalrelative to an FPGA clock; carrying out delay processing on the digital signal by using the delay parameter; and finally, synthesizing the front edge and the rear edge of the signal subjected to timedelay processing through logical operation to obtain an output pulse with accurate and adjustable time delay and width. According to the digital signal time delay method, the FPGA and the high-precision time delay chip are utilized, the digital signal time delay mode of combining coarse time delay with medium time delay and fine time delay is adopted, signal time delay jitter is effectively reduced, the time delay resolution is improved, most functions of the method are completed in one chip, a hardware circuit is simple and reliable, the integration degree is high, and the delay error is effectively reduced.

Description

technical field [0001] The invention belongs to the technical field of electronics, and in particular relates to a digital signal delay method based on an FPGA and a high-precision delay chip. Background technique [0002] In modern large-scale physical experiments, electronic equipment and instruments generally use electric pulse trigger signals to start and stop, or use pulse trigger signals to trigger a certain function of the test equipment in the test. figure 1 It is a schematic diagram of the device structure of an existing typical large-scale physical experiment. It can be seen from the figure that the positions of each equipment or instrument are different. The requirements for the time and width of the electrical pulse trigger signal input to the device or instrument are also different. In some experiments with higher requirements, the equipment and instruments not only require the time and width resolution of the trigger signal to reach 10 ps level, but also have ...

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Problems solved by technology

Therefore, although the delay resolution of this method can reach 10 ps level, its delay dynamic range is only a few microseconds, which cannot meet the requirements of large-scale physical experiments;

[0005] The second type is to use a field programmable logic gate array (FPGA) chip to build a coarse counter to realize the delay. This method has a large dynamic range of delay and can meet the experimental requirements, but because the resolution of the delay is determined by the rough counter Determined by the clock cycle, the clock cycle is often nanoseconds, so the resolution of this method is only nanoseconds

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