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FPGA receiving engine design based on SRIO

An engine, receiving state technology, applied in the field of signal processing, can solve problems such as complex design and inability to support real-time changes in the writing sequence

Active Publication Date: 2021-03-30
CHINA ELECTRONICS TECH GRP CORP NO 14 RES INST
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

If address mapping is not supported, the FPGA must customize a set of receiving logic for each write sequence, which cannot support real-time changes in the write sequence, making the design complex

Method used

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  • FPGA receiving engine design based on SRIO
  • FPGA receiving engine design based on SRIO
  • FPGA receiving engine design based on SRIO

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Embodiment Construction

[0029] The technical solution of the present invention will be specifically described below in conjunction with the accompanying drawings.

[0030] Because the SRIO transactions used by the CPU and DSP are generally NWRITE transactions and NWRITE_R transactions, the most commonly used is the transmission in units of double words, so only these two transactions are considered, and the transmission in units of words, halfwords, and bytes is not considered. .

[0031] In order to achieve high-efficiency reception, the present invention designs a mechanism for using DOORBELL transactions to terminate write operations. After the external master device initiates a series of SWRITE transactions or NWRITE transactions to the FPGA, it needs to initiate a DOORBELL transaction to terminate the write operation. Between FPGA and FPGA, set a special doorbell word 0x0033 as the doorbell identification for FPGA to recognize the notification of write operation termination.

[0032] The archit...

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PUM

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Abstract

The invention discloses an FPGA receiving engine design based on SRIO. The design adopts an SRIO receiving state machine, an SRIO write data packet receiving fifo, a write data packet merging state machine, a write command fifo, a write data fifo and a write memory state machine to form a receiving engine, adopts an SRIO logic layer to be connected with the SRIO receiving state machine, adopts a memory to be connected with the write memory state machine, and supports address mapping writing, and whether the SRIO data packet address is continuous or not is detected, so the single writing lengthof the memory is increased, the FPGA data receiving efficiency is improved, the mapping writing of the external main equipment to the FPGA internal address through the SRIO interface is realized, thefrequent switching of the memory access address is reduced, the memory access bandwidth is saved, and the FPGA data receiving efficiency is improved.

Description

technical field [0001] The invention belongs to the technical field of signal processing, and in particular relates to an FPGA design technology. Background technique [0002] The serial RapidIO bus, referred to as SRIO, is a bus interface specially designed for the interconnection of embedded systems. It has the advantages of fewer hardware pins, high transmission efficiency, low delay, low power consumption, and strong anti-interference ability. The maximum transmission rate of a single port is up to 25Gbps, and it is widely used in inter-chip and inter-board interconnections in embedded systems. communication. [0003] The SRIO protocol adopts a three-layer hierarchical architecture of logical layer, transport layer and physical layer: the top layer is the logical layer specification, which defines all transaction formats transmitted between endpoints; the middle layer is the transport layer specification, which defines how the exchange processing unit transmits The tra...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F12/06G06F13/42G06F15/17
CPCG06F12/063G06F13/4282G06F15/17Y02D10/00
Inventor 吴沁文
Owner CHINA ELECTRONICS TECH GRP CORP NO 14 RES INST
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