Gate-level netlist generation method and device and electronic device
A gate-level netlist and subsystem technology, applied in the field of gate-level netlist generation methods, devices and electronic equipment, can solve the problems of being prone to errors and time-consuming top-level gate-level netlists, so as to ensure generation efficiency and accuracy Effect
Active Publication Date: 2021-04-09
HYGON INFORMATION TECH CO LTD
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Problems solved by technology
[0005]In the prior art, usually the verifier manually generates the top-level design of the subsystem for gate-level simulation for each subsystem, so as to obtain the top-level gate-level net of the subsystem However, due to the large number of modules in the subsystem and each module usually has a large number of ports, the verifier manually generates the top-level design of the subsystem for gate-level simulation for each subsystem to obtain the The top-level gate-level netlist of the system is time-consuming and error-prone
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[0061] In order to make the purpose, technical solutions and advantages of the embodiments of the present application clearer, the technical solutions in the embodiments of the present application will be described below in conjunction with the drawings in the embodiments of the present application. In addition, it should be noted that like numerals and letters denote similar items in the following figures, therefore, once an item is defined in one figure, it does not need to be further defined and defined in subsequent figures. Explanation.
[0062] First, relevant explanations are given for the feedthrough signal and the feedthrough module proposed in the background art.
[0063] After completing the register transfer level (Register Transfer Level, RTL) top-level design of all subsystems in the chip and synthesizing it with the front-end, the chip needs to be physically designed, that is, the layout and routing design, and the layout and routing needs to be on the layout fo...
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The invention relates to the technical field of chip design, in particular to a gate-level netlist generation method and device and electronic device. The gate-level netlist generation method provided by the embodiment of the invention comprises the steps of obtaining port information of each module in a plurality of modules included in a target subsystem and instantiation information of each module in the plurality of modules, the plurality of modules comprising a function module and a feed-through module; obtaining register transmission level top layer design information of a target subsystem; and according to the port information of each module in the plurality of modules, the instantiation information of each module in the plurality of modules and the register transmission level top layer design information, packaging the plurality of modules including the function modules and the feed-through modules into a top layer design to obtain a top layer gate level netlist of the target subsystem. According to the gate-level netlist generation method and device and the electronic device provided by the embodiment of the invention, the generation efficiency and accuracy of the top gate-level netlist can be improved.
Description
technical field [0001] The present application relates to the technical field of chip design, in particular to a method, device and electronic equipment for generating a gate-level netlist. Background technique [0002] With the continuous advancement of semiconductor technology, the number of transistors that can be accommodated per unit chip area is increasing, and the chip size and design complexity are rapidly increasing geometrically. Especially system-level chips, which usually have ultra-high complexity. From the perspective of early chip design, for system-level chips, a hierarchical design method is generally used in the design process, that is, the design object is divided into Multiple subsystems, and each subsystem is divided into multiple modules with relatively independent functions for design. After the design of multiple modules is completed, they will be integrated according to the relationship between the modules, subsystems and system-level chips, and the...
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IPC IPC(8): G06F30/33G06F30/327G06F30/394G06F30/398
CPCG06F30/33G06F30/327G06F30/394G06F30/398
Inventor 谭帆王芳李冬梅焦瑞
Owner HYGON INFORMATION TECH CO LTD