Fault-tolerant architecture system and fault-tolerant architecture control method

A framework and network structure technology, applied in the field of fault-tolerant architecture, can solve the problems that the shortest distance of communication routers cannot always be used, and the load cannot be balanced, so as to achieve the effect of plastic reconstruction and integrity assurance

Inactive Publication Date: 2021-04-23
FUDAN UNIV
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  • Abstract
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Problems solved by technology

However, in the presence of failures, this scheme cannot always use the shortest distance between communicating routers when finding link paths, and cannot balance the load

Method used

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  • Fault-tolerant architecture system and fault-tolerant architecture control method
  • Fault-tolerant architecture system and fault-tolerant architecture control method
  • Fault-tolerant architecture system and fault-tolerant architecture control method

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Embodiment Construction

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention with reference to the accompanying drawings in the embodiments of the present invention. Obviously, the described embodiments are only some, not all, embodiments of the present invention. Based on the embodiments of the present invention, all other embodiments obtained by persons of ordinary skill in the art without making creative efforts belong to the protection scope of the present invention.

[0030] Such as figure 1 As shown, a structural conceptual schematic diagram of an AET cell cluster in a fault-tolerant architecture framework system provided by the present invention, a fault-tolerant architecture framework system includes a processing core unit and a peripheral unit, and the processing core unit is used for local calculation. The peripheral unit is used for global communication and system control, the processing core unit includes at least tw...

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Abstract

The invention discloses a fault-tolerant architecture system and a fault-tolerant architecture control method. The fault-tolerant architecture system comprises a processing core unit and a peripheral unit; the processing core unit is used for carrying out local computing, the peripheral unit is used for carrying out global communication and system control, the processing core unit comprises at least two AET cell clusters, each AET cell cluster comprises a central AET unit and three peripheral AET units, the network structures of the central AET unit and the peripheral AET units are the same, and the central AET unit of the AET cell cluster is connected with the three peripheral AET units at an included angle of 120 degrees; each AET unit of at least two AET cell clusters comprises three communication links, the processing core unit is configured with a connection strategy, and the connection strategy comprises that peripheral AET units in different AET cell clusters are connected with each other. The invention provides a fault-tolerant architecture system and a fault-tolerant architecture control method. A fault-tolerant architecture has a telescopic, highly reliable and flexible network structure.

Description

technical field [0001] The invention relates to the technical field of fault-tolerant architecture, in particular to a fault-tolerant architecture framework system and a fault-tolerant architecture control method. Background technique [0002] In modern electronic systems, whether it is at the chip level, board level, or even system level, when a certain part or even a certain unit fails, the entire system will be damaged or even fail. In order to ensure the integrity of data and system functions in the system, traditional fault tolerance strategies, such as multi-mode redundancy fault tolerance, error correction codes, etc.; the most widely used method in traditional fault tolerance methods is the use of redundant fault tolerance, which includes Hardware redundancy, time redundancy and information redundancy. Most of them use dual-redundancy or multi-redundancy systems to realize system backup, recovery and uninterrupted operation. For the dual-machine backup design, when...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H04L12/939H04L12/935H04L49/111
CPCH04L49/552H04L49/557H04L49/30
Inventor 刘力政邹卓郑立荣胡晓明
Owner FUDAN UNIV
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