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Integrated substrate structure, redistribution structure, and manufacturing method thereof

A manufacturing method and rewiring technology, applied in semiconductor/solid-state device manufacturing, electrical components, electrical solid-state devices, etc., can solve the problem that the circuit board is difficult to meet the terminal spacing and other problems

Pending Publication Date: 2021-05-18
胡迪群
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

As the level of integration increases, the number of terminals on highly integrated devices increases, making it difficult for circuit substrates to meet the pitch of terminals on such devices / wafers.

Method used

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  • Integrated substrate structure, redistribution structure, and manufacturing method thereof
  • Integrated substrate structure, redistribution structure, and manufacturing method thereof
  • Integrated substrate structure, redistribution structure, and manufacturing method thereof

Examples

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Embodiment Construction

[0075] Reference will now be made in detail to the exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers are used in the drawings and descriptions to refer to the same or like parts.

[0076] Figure 1A to Figure 1J is a schematic cross-sectional view of a method of fabricating an integrated substrate structure according to some embodiments. Please refer to Figure 1A , providing a temporary carrier 50 with a release layer 51 . The temporary carrier 50 can be made of glass (glass), plastic (plastic), silicon (silicon), metal (metal) or other suitable materials, as long as the material can support the structures formed thereon in subsequent processes That's it. In some embodiments, the release layer 51 (for example, a light to heat conversion film or other suitable de-bonding layer) applied on the temporary carrier 50 can be subsequently The releasability of subsequently ...

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Abstract

The invention provides an integrated substrate structure, including a redistribution film, a circuit substrate, and a plurality of conductive features. The redistribution film includes a fine redistribution circuit, and the circuit substrate is disposed over the redistribution film and includes a core layer, and a coarse redistribution circuit disposed within and on the core layer. The circuit board is thicker and stiffer than the wiring film, and the layout density of the fine redistribution circuits is denser than the layout density of the coarse redistribution circuits. A conductive feature is interposed between the circuit substrate and the redistribution film to connect the fine redistribution circuit and the coarse redistribution circuit. The invention also provides a redistribution structure and a manufacturing method. The integrated substrate structure, the redistribution structure and the manufacturing method thereof can be used for connecting / testing semiconductor wafers with fine pitch terminals so as to meet the requirements of reliability, good electrical performance, thinness, rigidity, planeness, competitive unit price and the like.

Description

[0001] Cross References to Related Applications [0002] This application claims the benefit of U.S. Provisional Patent Application No. 62 / 935,641, filed November 15, 2019, and U.S. Patent Application No. 17 / 024,676, filed September 17, 2020, which are incorporated by reference in their entirety into this article. technical field [0003] The invention relates to an integrated substrate structure, a rewiring structure and a manufacturing method thereof, in particular to an integrated substrate structure for coupling / testing semiconductor devices, a rewiring structure with fine circuits and a manufacturing method thereof. Background technique [0004] With the rapid development of the electronic industry, the development trend of semiconductor die has been gradually towards miniaturization and integration. With the improvement of integration level, the number of terminals on highly integrated devices increases, making it difficult for circuit substrates to meet the pitch of ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): H01L23/498H01L21/48
CPCH01L23/49838H01L21/4846H01L24/02H01L2224/0231H01L2224/02331H01L2224/02373
Inventor 胡迪群
Owner 胡迪群