Parallel multiplier and working method thereof
A multiplier and carry adder technology, which is applied in the field of parallel multipliers, can solve the problems of timing difference and large area of parallel multipliers, and achieve the effect of improving timing, reducing circuit area, and meeting high-performance timing requirements
Active Publication Date: 2021-05-28
TSINGHUA UNIV
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Problems solved by technology
[0005] The embodiment of the present invention provides a parallel multiplier to solve the technical problems of large parallel multiplier area and poor timing in the prior art
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[0031] In order to make the object, technical solution and advantages of the present invention clearer, the present invention will be described in further detail below in conjunction with the embodiments and accompanying drawings. Here, the exemplary embodiments and descriptions of the present invention are used to explain the present invention, but not to limit the present invention.
[0032] In an embodiment of the present invention, a parallel multiplier is provided, such as figure 2 As shown, the parallel multiplier consists of:
[0033] Codec circuit 202, for NR4SD + The digital set is encoded and decoded to obtain a partial product array;
[0034] A reduced tree structure 204, connected to the encoding and decoding circuit, for performing accumulation processing on the parts in the partial product array except the last two partial product rows;
[0035] The improved square root select carry adder 206 is connected to the reduced tree structure and is used to perform a...
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The embodiment of the invention provides a parallel multiplier and a working method thereof, and the parallel multiplier comprises a coding and decoding circuit which is used for carrying out the coding and decoding of a digital set of NR4SD +, and obtaining a partial product array; a reduction tree structure which is connected with the coding and decoding circuit and is used for carrying out accumulation processing on parts except the last two partial product rows in the partial product array; an improved square root selective carry adder which is connected with the reduction tree structure and is used for carrying out addition processing on the last two partial product rows of the partial product array, wherein the improved square root selective carry adder comprises a full adder, a half adder and a first customized combination circuit, and the first customized combination circuit comprises a digital circuit device. According to the scheme, the time sequence can be improved, meanwhile, the area is reduced, and the parallel multiplier can meet the high-performance time sequence requirement.
Description
technical field [0001] The invention relates to the technical field of digital signal processing, in particular to a parallel multiplier and its working method. Background technique [0002] Digital multipliers are widely used in microprocessors, multimedia and digital signal processors, and other products. Typical DSP functions include convolution, digital filtering, and signal conversion; these functions require various multipliers. In addition, in chips based on intelligent architecture, a large number of multipliers and multiply-adders are required. Therefore, a general-purpose multiplier with superior performance (thereby deriving other sub-multipliers) is urgently needed by industry and academia. The criteria for measuring the performance of the multiplier include: critical path delay, area, power consumption, power consumption delay product, area delay product, etc. [0003] Current multipliers include serial multipliers and parallel multipliers. However, the timi...
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Login to View More IPC IPC(8): G06F7/523
CPCG06F7/523Y02D10/00
Inventor 尹首一段宁远韩慧明刘雷波魏少军
Owner TSINGHUA UNIV