Interface system for interconnecting bare core and MPU and communication method thereof

A communication method and technology of an interface system, which are applied in the field of interface systems for interconnecting bare cores and MPUs, can solve problems such as difficulty in use, poor versatility, and complex technical systems, and achieve the effect of reducing complexity and small amount of data.

Active Publication Date: 2021-05-28
58TH RES INST OF CETC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The existing communication protocols for multi-core integration are either dedicated protocols with poor versatility; or the technical system is too complex and difficult to use

Method used

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  • Interface system for interconnecting bare core and MPU and communication method thereof
  • Interface system for interconnecting bare core and MPU and communication method thereof
  • Interface system for interconnecting bare core and MPU and communication method thereof

Examples

Experimental program
Comparison scheme
Effect test

Embodiment 1

[0041] Such as figure 1 with figure 2 As shown, the interface system of interconnecting the bare core and the MPU includes: a data interface, an interrupt interface and a debugging interface; Self-starting, the DMA control interface is used for DMA start and end control; the interrupt interface is used to receive the interrupt data packet from the network and analyze the pulse interrupt input required by the MPU, and the interrupt interface receives the interrupt address operation from the data interface at the same time And it is converted into an interrupt event and sent; the debug interface includes a JTAG-Core debug interface, which is used to receive a debug packet from the network and translate it into a JTAG protocol for MPU debugging.

[0042] The SPI interface, DDR data interface, DMA control interface and interrupt interface are connected to the same router in the interconnected bare core; the debugging interface is connected to another router in the interconnected...

Embodiment 2

[0052] The communication method between the interconnected bare core and the MPU, data transmission is performed between the interconnected bare core and the MPU through a data interface, interrupt transmission is performed through an interrupt interface, and MPU debugging is performed through a debugging interface; the MPU controls two or two MPUs through a DMA control interface The data access between the above slave devices is controlled; the data interface includes an SPI interface, a DDR data interface and a DMA control interface; the debugging interface includes a JTAG-Core debugging interface.

[0053] The MPU sends a memory access request to the interconnected bare core in the DDR data format through the data interface; the interconnected bare core converts the response data packet into the DDR data format and sends it to the MPU.

[0054] When the MPU sends a request event to the interconnected bare core, a request packet is generated, and the generation of the request...

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Abstract

The invention relates to an interface system for interconnecting a bare core and an MPU and a communication method thereof. The interface system for interconnecting the bare core and the MPU comprises a data interface, an interrupt interface and a debugging interface; the data interface comprises an SPI, a DDR data interface and a DMA control interface, the SPI is used for autonomously starting the MPU in a starting stage, and the DMA control interface is used for controlling DMA starting and ending; the interrupt interface is used for receiving an interrupt data packet from a network and analyzing the interrupt data packet to obtain pulse interrupt input required by the MPU, and meanwhile, the interrupt interface receives an interrupt address operation from the data interface and converts the interrupt address operation into an interrupt event to be sent out; the debugging interface comprises a JTAG-Core debugging interface and is used for receiving a debugging data packet from a network and translating the debugging data packet into a JTAG protocol for MPU debugging. According to the system, an interface provided by an interconnection bare core is correspondingly interconnected with a master device MPU interface through an interrupt interface, a DDR data interface, an SPI interface and a JTAG-Core debugging interface, and extension of the MPU in the high-performance information processing microsystem and high-speed communication between the MPU and the interconnection bare core are achieved.

Description

technical field [0001] The invention relates to a communication interface, in particular to an interface system and a communication method for interconnecting bare cores and MPUs. Background technique [0002] In a monolithic ASIC, all components are designed and manufactured on a silicon chip with the same process. As process geometries shrink, the cost and cycle time to develop such integrated circuits becomes extremely high. In this case, multi-core integration is an inevitable choice, that is, to interconnect and assemble multiple verified and unpackaged chip components with different functions, and package them as a whole chip in the same package to form a package Level network NoP (Network on Package). These bare cores can use different processes and come from different manufacturers, thus greatly shortening and reducing the development cycle and difficulty. The difficulty of multi-die integration lies in how to efficiently interconnect each die and ensure high micr...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F13/42G06F13/40G06F15/78H04Q1/02
CPCG06F13/4282G06F13/4031G06F15/7825H04Q1/028G01R31/31705G01R31/318547G01R31/318555G01R31/318597
Inventor 魏敬和黄乐天肖志强冯敏刚丁涛杰郑利华
Owner 58TH RES INST OF CETC
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