40results about How to "Realize high-speed communication" patented technology

The invention relates to a safety isolation file transmission control method, in particular to a file transmission control method between taxation network safety isolation systems. A transmission control system comprises an external network isolation firewall, an external network control end, an external network transmitting end, an external network receiving end, an internal network transmitting end, an internal network receiving end, an internal network control end and an internal network isolation firewall. A computer system, a virtual machine system and the isolation firewalls are combined to achieved a relatively universal safety data transmission manner, safe and reliable bidirectional data transmission is achieved by the control method with a special safety protocol, confidentiality, completeness and non-repudiation during information transmission are achieved by safety techniques such as data encryption, digital signatures and information authentication codes, data exchanging performance is increased while safety of internal and external network systems is guaranteed, and the whole system can work reliably and stably.

The invention relates to the field of wireless network high-speed switching and high bandwidth communication under mobile environment, which aims at solving the technical problem of a system and a method for realizing bandwidth communication between highway vehicles, wherein, the system comprises base stations distributed and installed along the roadsides of highways and on-board wireless communication terminals, which all comply with the WLAN wireless access 802.11a/b/g/p standard, the base stations are connected by optical fibers to form a local area network, the on-board wireless communication terminal is also provided with the global positioning system (GPS) function. The on-board wireless communication equipment can synchronously establish radio links with a plurality of roadside base stations so as to realize the high bandwidth communication, the transmission rate of which is higher than the previous transmission rate by a plurality of times. When passing through the covered areas of different base stations at high speed, the vehicle can adopt the self-adaption rate selection and self-adaption flow method to gradually disconnect the links with gradually weak wireless signals, and establish the new links with gradually strong signals in sequence or in a great-leap-forward mode, thus realizing steady and extremely soft network switch, and ensuring communication continuity. The method supports the high-speed mobility of the vehicle, the multimedia broadband service of the mobile equipment and the large-scale network coverage, and realizes the bandwidth communication of highway vehicles.

The invention discloses a task driven dynamic adaptive environment sensing mobile robot, system and method. The method comprises the steps that S1) a cloud server generates a sensing task according toinformation including the geographic position of each sensing area and parameters need to be sensed for the mobile robot; S2) the mobile robot obtains the sensing task from the cloud server in real time, adjusts the sensing area and a corresponding environment sensor dynamically according to the sensing task so as to sense the corresponding environment parameters, and complete the corresponding environment sensing task; and S3) the mobile robot sends the collected environment parameters to the cloud server in real time. The cloud serer adjusts the environment sensing parameters of the mobilerobot dynamically according to the geographic or spatial position of the cloud server, so that the mobile robot can sense the corresponding environment parameters according to different environments and unnecessary energy consumption is reduced.

The invention discloses a DSP based Ethernet communication method in a fault recording system, comprising the following steps of: (1) after a message interrupt service routine is received, storing received messages into Pbufs chain buffers, also sequentially storing pointers of the chain buffers storing the messages into a self-defined received message circulating array without directly transmitting to a protocol stack, when the messages are completely received, interrupting the service routine, i.e. quitting; (2) transmitting the messages inside the circulating array to a 1wIP protocol stack for demultiplex; (3) inputting application layer data; (4) outputting the application layer data; (5) encapsulating the messages written into a buffering area of a transmission layer of the protocol stack into network messages; (6) writing the network messages into an Ethernet controller, and transforming data frames into differential signals to be transmitted to a network by the Ethernet controller. The DSP based Ethernet communication method in the fault recording system can realize that the data information of the fault recording system is fast communicated through the Ethernet.

The invention discloses a point-to-point on-chip communication module based on interruption. The point-to-point on-chip communication module comprises an AXI (Advanced eXtensible Interface) protocol conversion module, an intersection queue communication module and an interruption management module. A traditional structure for communicating by a shared storage mode is changed; point-to-point communication modules arrayed in a full array are adopted, so that software overhead is reduced, resource consumption is reduced, all parallel work of master devices is realized, and the parallelism and the efficiency are improved. The point-to-point communication is realized by adopting an interruption mode, so that the defect that a query mode occupies the cycle of a CPU (Central Processing Unit) is effectively overcome. By adopting an intersection queue type structure, the shaking closed loop considered as bottleneck of on-chip communication network performances is broken, and the low-delay communication performance is realized; point-to-point is realized on the basis of asynchronous FIFO (First Input First Output), a local synchronization and integral asynchronization mode is realized, and cross clock domain processing is realized. The asynchronous FIFO adopts a shallow FIFO based on a register file; communication delay is smaller than an on-chip SRAM (Static Random Access Memory) structure of a shared storage and is effectively reduced, and high-speed communication is realized.

The present invention relates to a communication device comprising at least one channel unit. Each channel unit comprising a first interface unit, a second interface unit, a first FIFO unit, a secondFIFO unit, and a storage unit. The first interface unit comprises a first control register, and the first control register is suitable for receiving quantity information and position information of to-be-transmitted data. The second interface unit comprises a second control register, and the second control register is suitable for receiving the quantity information of the to-be-transmitted data from the first control register and receiving the position information of the storage area allocated to the to-be-transmitted data by the receiving end. The first FIFO unit is connected with the first interface unit and is suitable for acquiring quantity information and position information of to-be-transmitted data from the first control register. The second FIFO unit is connected with the second interface unit, and is suitable for obtaining the quantity information of the to-be-transmitted data from the second control register. And the storage unit is connected with the first FIFO unit and thesecond FIFO unit.

The invention relates to an interface system for interconnecting a bare core and an MPU and a communication method thereof. The interface system for interconnecting the bare core and the MPU comprises a data interface, an interrupt interface and a debugging interface; the data interface comprises an SPI, a DDR data interface and a DMA control interface, the SPI is used for autonomously starting the MPU in a starting stage, and the DMA control interface is used for controlling DMA starting and ending; the interrupt interface is used for receiving an interrupt data packet from a network and analyzing the interrupt data packet to obtain pulse interrupt input required by the MPU, and meanwhile, the interrupt interface receives an interrupt address operation from the data interface and converts the interrupt address operation into an interrupt event to be sent out; the debugging interface comprises a JTAG-Core debugging interface and is used for receiving a debugging data packet from a network and translating the debugging data packet into a JTAG protocol for MPU debugging. According to the system, an interface provided by an interconnection bare core is correspondingly interconnected with a master device MPU interface through an interrupt interface, a DDR data interface, an SPI interface and a JTAG-Core debugging interface, and extension of the MPU in the high-performance information processing microsystem and high-speed communication between the MPU and the interconnection bare core are achieved.

The invention provides a composite semiconductor layer which comprises a silicon-on-insulator (SOI) substrate and a filed effect transistor. The SOI substrate is deposited on a bulk silicon material, and a silicon film is deposited on the SOI substrate. The field effect transistor is arranged on the silicon film, a source electrode of the field effect transistor is connected onto a second auxiliary input/output signal line through a first via hole, the second auxiliary input/output signal line is connected onto a first auxiliary input/output signal line through a third via hole, a drain electrode is connected onto a first metal electrode through a second via hole, the first metal electrode is connected onto a second metal electrode through a fourth via hole, one end of the second metal electrode is connected onto a second input/output signal line through a first through hole, and a ferroelectric layer, an antiferromagnetic layer, a lower ferromagnetic layer, a tunnel insulating barrier layer, an upper ferromagnetic layer and a top cover layer are sequentially deposited at the other end of the second metal electrode. The antiferromagnetic layer is connected onto a third input/output signal line through a second through hole, and the top cover layer is connected onto the first input/output signal line through a fifth via hole.

The invention discloses a programmable NoC 10-gigabit Ethernet resource network interface system. The programmable NoC 10-gigabit Ethernet resource network interface system comprises a network interface module, a data processing module, a receiving module, an error management module and a protocol support module, and the advantages of high compatibility and long transmission distance of 10-gigabitEthernet are utilized to realize high-efficiency communication between routing nodes and a high-performance processor on a network-on-chip. Through the configuration port, the configuration of the source address and the destination address of each layer of the network and the configuration work of the error management function are realized; and support to the UDP/IP protocol is provided, and a resource network interface structure with protocol support and higher efficiency is designed to realize high-efficiency interconnection between the routing node and the high-speed data transmission interface, so that the purpose of data exchange between the network-on-chip and the high-performance processor is achieved.

The embodiment of the invention discloses a communication system and method. The system comprises a master device, a signal processing device and at least one slave device. The main devicet is used for generating a data signal in a set format when a data sending condition is met, and sending the data signal to the signal processing device through a data output pin; the signal processing device is used for generating an integer clock signal according to the data signal, sending the data signal to each slave device through the data output pin, and sending the integer clock signal to each slave device through the counting pin; each slave device is used for receiving the data signal according to the integer clock signal, wherein the data signal comprises at least one piece of byte length information and byte data information corresponding to each piece of byte length information, and the quantity of the byte length information is determined by the quantity of the slave devices, so that the problem that chip selection signals must be sent to the slave devices in the communication process of the master device and the slave devices in the prior art is solved; the effect of high-speed communication between the master device and the slave device is achieved.

The invention discloses an underwater non-contact type communicator which comprises a sealing cavity, a wireless network card, a wireless transmission circuit and a battery, wherein the wireless network card, the wireless transmission circuit and the battery are arranged in the sealing cavity; a network card antenna extends into the cavity from a front end cover of the sealing cavity to be connected with the wireless network card, a pressure-resisting antenna protective jacket is sleeved on the network card antenna, and a watertight connector is arranged on a rear end cover of the sealing cavity; the wireless transmission circuit comprises an ARM9 (Advanced RISC (Reduced Instruction-Set Computer) Machine) chip module, a serial communication module, a power supply module, a USB interface module, a JTAG (Joint Test Action Group) interface module and an SD (Secure Digital Memory) card module; the serial communication module, the power supply module, the USB port module, the JTAG port module and the SD card module are connected with the ARM9 chip module; the wireless network card is connected to the USB port module, the serial communication module and the power supply module are both connected with the watertight connector, and the other port of the power supply module is connected with the battery. The underwater non-contact communicator has the advantages of simple structure, reliable work, simple control and capability of realizing high-speed communication between devices in a deep sea high-pressure environment.

The invention discloses an integrated astronomical data acquisition and storage system based on a persistent memory. The system comprises a data acquisition end, a communication module and a data storage end which are in communication connection in sequence, the data acquisition end is used for acquiring astronomical data observed by the astronomical telescope for persistent storage; the communication module is used for transmitting the astronomical data in buffer to the data storage end after the astronomical data in persistent storage is fully buffered; and the data storage end is used for persistently storing the astronomical data transmitted by the communication module. According to the invention, a persistent storage mode is used to realize high-speed acquisition of the data in the memory and transmission of the data to the storage end, so that the data is not lost in case of abnormality, the reliability of the acquisition system is greatly improved, and the safety of astronomicalobservation data is also improved.

The invention provides a network interface design and communication method for an extensible interconnection bare core and peer-to-peer equipment, the network interface NI facing the peer-to-peer equipment is composed of a protocol converter and an event controller, and the protocol converter comprises a Shell, a Buffer and a Kerne. The Shell is a local bus protocol controller and can complete format conversion and data receiving and transmitting according to a peer-to-peer device interface bus format and a data packet transmission data format; the Buffer is used for data buffering and clock domain isolation; the Kernel is mainly used for completing data packing and unpacking work; the event controller is mainly used for managing and organizing request and response events, ensuring one-to-one correspondence between requests and responses, and avoiding loss of data packets. Meanwhile, the invention provides an interface design scheme based on an Initiator/Target mode and a CondensedI/O mode, and expansion of the peer-to-peer equipment in the high-performance information processing microsystem and high-speed communication between the peer-to-peer equipment and the interconnection bare core can be realized by interconnecting the peer-to-peer interface provided by the interconnection bare core and the peer-to-peer interface of the peer-to-peer equipment.

The invention provides a neutrino communication device. The neutrino communication device comprises a heating device, a hydrogen ion accelerator, a beryllium target and a receiving device. The beryllium target is arranged over against the output port of the hydrogen ion accelerator; The heating device is used for pyrolyzing tap water to obtain a hydrogen source and transmitting the hydrogen sourceto the hydrogen ion accelerator; The hydrogen ion accelerator receives the modulation signal, modulates the hydrogen source according to the modulation signal, accelerates the modulated hydrogen source, and uses the proton beam obtained after acceleration to hit a beryllium target; The receiving device is of a hollow structure with an opening, and the opening of the receiving device faces the beryllium target. And water and a photomultiplier are arranged in the receiving device, and the photomultiplier receives an optical signal which is transmitted by the microcells of the proton beam and passes through the water, demodulates the optical signal into an electric signal and outputs the electric signal. According to the neutrino communication device, cables, optical fibers and the like do not need to be laid in advance, high-speed communication can be achieved anytime and anywhere, and the application range is wide.

The invention discloses a Chirp signal generator, a Chirp communication system and a method for generating a Chirp signal. The Chirp signal generator comprises a voltage-controlled oscillator, a phasediscriminator, a loop filter and an adder. The voltage-controlled oscillator is used for outputting a Chirp signal, and the oscillation frequency of the voltage-controlled oscillator can be adjustedso as to control the phase or frequency of an output signal of the voltage-controlled oscillator. The phase discriminator receives the first input signal and compares phases of the first input signaland the output signal of the voltage-controlled oscillator, and generates a first signal. The loop filter filters a high-frequency signal and a noise signal from the first signal to generate a secondsignal. And the adder receives the second input signal and superposes the second signal and the second input signal to generate a third signal, and the third signal controls the voltage-controlled oscillator to adjust the oscillation frequency. Wherein the second input signal is a triangular wave signal and comprises a plurality of triangular wave symbols with the same frequency waveform, and thesymbol starting point and the symbol ending point are the same in frequency. The transition time for generating the Chirp signal is shorter, and the method can be applied to high-speed communication.

The application provides a chip interconnection structure, a chip and a chip interconnection method. The chip interconnection structure includes a first chip and at least one second chip, wherein theswitching face of the first chip is opposite to the switching face of the second chip, at least one conducting component is arranged between the second chip and the first chip, every conducting component includes at least one electrically conductive piece connected between the bonding pad of the second chip and the bonding pad of the first chip. The chip interconnection structure can make two or more chips interconnected and communicate with each other at a high speed.