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Data exchange system of high-speed storage interface IP (Internet Protocol) core based on MPMC (Multi-Port Memory Controller)

A memory interface and data exchange technology, applied in the direction of electrical digital data processing, instruments, etc., can solve the problems of low utilization rate of IP core resources and data throughput rate, and improve resource utilization rate, data throughput rate, and resource utilization rate , The effect of improving throughput

Active Publication Date: 2014-07-30
哈尔滨诺信工大测控技术有限公司
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

[0003] The purpose of the present invention is to provide a data exchange system based on MPMC-based high-speed memory interface IP core in order to solve the problem that the current data exchange system realizes the relatively low utilization rate of IP core resources and data throughput of off-chip memory access

Method used

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  • Data exchange system of high-speed storage interface IP (Internet Protocol) core based on MPMC (Multi-Port Memory Controller)
  • Data exchange system of high-speed storage interface IP (Internet Protocol) core based on MPMC (Multi-Port Memory Controller)
  • Data exchange system of high-speed storage interface IP (Internet Protocol) core based on MPMC (Multi-Port Memory Controller)

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specific Embodiment approach 1

[0015] Specific implementation mode one: combine figure 1 and figure 2 Illustrate the present embodiment, the data exchange system of the high-speed memory interface IP core based on MPMC of the present invention, it comprises user logic module 1, MPMC IP core module 2 and interface IP core module 3; UBus bus 4 is connected with the first control bus of interface IP core module 3, the second control bus of interface IP core module 3 is connected with the first control bus of MPMC IP core module 2 by NPI bus 5, the first control bus of MPMC IP core module 2 2. The control bus is connected with the off-chip memory;

[0016] The interface IP core module 3 includes a read control module 3-1, a selection module 3-2 and a write control module 3-3, and the first control bus of the read control module 3-1 and the first control bus of the write control module 3-3 are respectively It is connected with the custom UBus bus 4, the second control bus of the read control module 3-1 is con...

specific Embodiment approach 2

[0019] Specific implementation mode two: combination image 3 Describe this embodiment, the difference between this embodiment and specific embodiment 1 is that its read control module 3-1 includes read data FIFO module 3-1-1, read data module 3-1-2, read mode and request control Module 3-1-3, selection switch module 3-1-4 and address generator 3-1-5;

[0020] The read data FIFO module 3-1-1 sends the data bus signal Rd_data of the read interface to the data bus signal input end of the read interface of the custom UBus bus 4;

[0021] The custom UBus bus 4 sends the read enable signal Rd_en to the input end of the read enable signal of the read data FIFO module 3-1-1;

[0022] The read data FIFO module 3-1-1 sends the read interface data valid signal R_valid to the input terminal of the read interface data valid signal of the custom UBus bus 4;

[0023] The read data FIFO module 3-1-1 sends the signal Num of the number of data remaining in the read data FIFO to the signal of...

specific Embodiment approach 3

[0048] Specific implementation mode three: combination Figure 4 Describe this embodiment, the difference between this embodiment and specific embodiment one is that its write control module 3-3 includes write data FIFO module 3-2-1, write start and write mode judgment module 3-2-2, write sequence Control module 3-2-3 and write address generator 3-2-4;

[0049] The custom UBus bus 4 sends the write enable signal Wr_en of the write data to the write enable signal input end of the write data FIFO module 3-2-1;

[0050] The custom UBus bus 4 sends the data bus signal Wr_data of the write data to the data bus signal input end of the write data FIFO module 3-2-1;

[0051] Write data FIFO module 3-2-1 sends the permission signal W_permit of writing data to the permission signal input terminal of writing data of custom UBus bus 4;

[0052] The custom UBus bus 4 sends the write completion signal Fsh_wr to the write start and write mode judgment module 3-2-2 write completion signal i...

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Abstract

The invention discloses a data exchange system of a high-speed storage interface IP (Internet Protocol) core based on an MPMC (Multi-Port Memory Controller), which relates to a data exchange system and is used for solving the problems of low IP core resource utilization ratio and data throughput during realization of an off-chip storage by using the data exchange system. A user logic module control bus is communicated with an interface IP core through a customized UBus bus; the interface IP core is communicated with the MPMC IP core through an NPI (Numbering Plan Identifier) bus; the MPMC IP core is communicated with the off-chip storage; the interface IP core comprises a reading control module, a selection module and a writing control module; a first control bus of the reading control module and a first control bus of the writing control module are connected with the customized UBus bus respectively; a second control bus of the reading control module is connected with a first control bus of the selection module; a second control bus of the writing control module is connected with a second control bus of the selection module; and a third control bus of the reading control module and a third control bus of the writing control module are connected with the NPI bus respectively. The data exchange system is used for exchanging data with the off-chip storage.

Description

technical field [0001] The invention relates to a data exchange system, in particular to a data exchange system based on MPMC high-speed memory interface IP core. Background technique [0002] In the data exchange system, the excellent design of off-chip memory access and control can improve the performance and development speed of the system. Using a dedicated memory controller IP (Intellectual Property) core to complete access to off-chip memory is a common method in FPGA application design, such as Altera's DDR Controller IP core and Xilinx's MPMC (Multi-Port Memory Controller, multi-port memory control device) IP core, etc. The MPMC IP core has high versatility and supports a variety of user interfaces. Under the NPI (Native Port Interface) bus interface, it has a variety of transmission modes with different efficiencies, causing it to have different burst transmission lengths and addresses in different modes. Different restriction requirements increase the difficulty ...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): G06F13/16
Inventor 王少军刘大同彭宇仲雪洁庞业勇马宁
Owner 哈尔滨诺信工大测控技术有限公司
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