Model order reduction method and device of delay circuit system and medium

Abstract

The invention discloses a model order reduction method of a delay circuit system. The method comprises the following steps: establishing a corresponding delay circuit model based on a circuit structure and circuit parameters of a delay circuit; performing Laplace transformation on the delay circuit model to obtain a first transfer function; obtaining a delay term based on the first transfer function; obtaining a delay function and a transformation factor based on the Hermite polynomial and the delay term; acquiring a transformation function based on the delay function and the transformation factor, and setting a recursive relational expression based on the transformation function; carrying out orthogonalization processing based on an orthogonal algorithm and a recursive relational expression to obtain a projection matrix; and performing projection transformation on the delay circuit model based on the projection matrix to obtain a reduced-order model of the delay circuit. According to the method and device, the Hermite polynomial can be used for carrying out order reduction processing on the model of the high-speed interconnection circuit system, the order reduction standard of the high-speed interconnection circuit system is met, the passivity and the structural property of the circuit system before order reduction are guaranteed, and then the stability of the circuit system after order reduction is improved.

Description

technical field [0001] The invention relates to the technical field of integrated circuit design, in particular to a model order reduction method, device and medium of a delay circuit system. Background technique [0002] When designing an integrated circuit, it is necessary to design the interconnection line, and the delay should be considered in the design of the interconnection line. Therefore, it is necessary to model and analyze the interconnected delay circuit system, and then obtain the corresponding differential equation model containing the delay term; Existing interconnection delay circuits are large in scale, so it is necessary to reduce the order of the differential equation model; [0003] There are two existing order reduction methods: the first is to use the linear system model order reduction to process the delay items after Taylor expansion in the differential equation model; the second is to use the Gramian(gram matrix, which is the Gram matrix ) matrix to...

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Problems solved by technology

[0004] The present invention mainly solves the problem that the passivity and structure of the circuit system before the order reduction cannot be guaranteed when the interconnected delay circuit system performs model reduction.

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