Single input single output RCS interconnection circuit degradation method

A single-input, single-output, interconnected circuit technology, applied in the electronic field, can solve the problems that the system cannot be matched accurately, and the moment matching accuracy cannot be guaranteed.

Inactive Publication Date: 2005-04-06
FUDAN UNIV
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

Therefore, the reduced-order system obtained by SMOR cannot exactly match the moments of the original system, and the moment matching accuracy cannot be guaranteed

Method used

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  • Single input single output RCS interconnection circuit degradation method
  • Single input single output RCS interconnection circuit degradation method
  • Single input single output RCS interconnection circuit degradation method

Examples

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Embodiment Construction

[0118] The present invention is further illustrated below by specific examples.

[0119] right figure 1 The 8-bit bus circuit shown (including two shielded wires) can be obtained by using the corresponding parameter extraction tool to obtain an equivalent RCS circuit. There are 490 unknown variables in the equivalent circuit, including 330 node voltages and 160 susceptance currents. We use the frequency response of node A as a measure of the accuracy of the order reduction.

[0120] First, we use the algorithm of the present invention to reduce the order of the original circuit to different orders, namely 40, 60, and 80, and compare the accuracy of the order reduction. figure 2 It is a comparison chart of the frequency response curve of the original system and the frequency response curve of the reduced-order system of different orders obtained by SAPOR of the present invention. image 3 It is the error comparison of the frequency response of the reduced-order system with ...

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Abstract

This invention belongs to electron technique field, which is in detail single input and output RCS connection circuit based on second order Arnoldi process. The method comprises the following steps: to form second order system, system frequency shift, system linearization, getting orthogonal matrix Q o f Krylov sub-space; finally to get N order deduction system. This invention is characterized by the following: it has high accuracy and ensures the data stability of the order deduction and has low computation and storage and ensures the passivity of the order deduction system.

Description

technical field [0001] The invention belongs to the field of electronic technology, and in particular relates to a model reduction method for a linear circuit. technical background [0002] Integrated circuits have been developed to the point where electronic systems containing more than 1 billion devices can be integrated on a single chip, that is, System on One Chip (SOC). For millions of large-scale circuits, how to quickly and accurately simulate and verify the correctness of its design within a reasonable time has become a bottleneck in the design of system-on-chip (SOC). According to statistics, the time for SOC chip simulation verification has accounted for 70% of the entire design time. [0003] In the ultra-high-speed ultra-deep sub-micron SOC design, the performance of interconnect lines greatly affects the performance of the entire chip. Crosstalk and delay problems when signals propagate on interconnect lines may cause timing deviations, logic errors, and even ...

Claims

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Application Information

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Patent Type & Authority Applications(China)
IPC IPC(8): G06F17/50
Inventor 曾璇苏仰锋王健刘榜
Owner FUDAN UNIV
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