A method and system for improving time stamp accuracy

Abstract

The invention discloses a method and system for improving the accuracy of time stamps, and relates to the field of time synchronization. The method includes sending a second pulse signal or a frame positioning identification signal output by an OTN service processing chip to an LVDS SERDES interface of FPGA; through the LVDS SERDES interface Get the rising edge position of the frame positioning identification signal, and generate a real-time time sampling indication signal at the same time, and take the current real-time time as the initial time stamp T; based on the non-zero sampling value corresponding to the real-time time sampling indication signal, generate a sampling error compensation value △ t1; the current oversampling state is obtained based on the statistical results, and different oversampling states correspond to different oversampling error compensation values ​​△t2, then the final timestamp is equal to the initial timestamp T, sampling error compensation value △t1 and oversampling error The sum of the compensation value △t2. The invention is simple to implement and has lower requirements on the timing sequence of the FPGA device.

Description

technical field [0001] The invention relates to the field of time synchronization, in particular to a method and system for improving the accuracy of time stamps. Background technique [0002] Time stamp is one of the key elements of time synchronization. The 1588 protocol stipulates the method and requirements of time stamping. For event messages, time stamping is required when receiving and sending, which is convenient for calculating line delay. The jitter that causes the line delay is large, which will affect the performance index of time synchronization. With the advent of the 5G (5th generation mobile networks, fifth-generation mobile communication technology) communication era, 5G communication poses new requirements and challenges for time synchronization technology, and improving the accuracy of time stamps is the key to meeting new requirements. When maintaining real-time time or processing time stamps, a 125MHz clock is usually used to sample the second pulse sig...

AI Technical Summary

Problems solved by technology

[0003] Commonly used methods to improve timestamp accuracy include increasing sampling clock frequency and multi-phase sampling. For FPGA (Field-Programmable Gate Array, Field Programmable Gate Array), the clock frequency can usually be increased to about 250MHz-300MHz, and then continue There is not much room to increase the frequency of the sampling clock; for the method of multi-phase sampling, because the routing of the clock and data in the FPGA is not easy to control accurately, resulting in large errors, the actual implementation effect is not ideal

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