Clock duty cycle calibration circuit

Abstract

The invention relates to a clock duty ratio calibration circuit, and the circuit comprises a duty ratio adjustment circuit which is used for adjusting the duty ratio of an input clock signal based on a control word determined by a digital control logic circuit; a duty ratio detection circuit which is connected with the output end of the duty ratio adjusting circuit and is used for detecting the adjusted clock duty ratio; a digital control logic circuit which is connected with the duty ratio detection circuit and the duty ratio adjustment circuit and is used for determining a control word according to the adjusted clock duty ratio, wherein the control word is used for indicating the duty ratio adjustment circuit to adjust the duty ratio of the input clock signal. According to the clock duty ratio calibration circuit and the clock duty ratio calibration method, the problems of relatively low precision and relatively narrow calibration range of a clock duty ratio calibration circuit in related technologies are solved, and the effects of improving the precision of the clock duty ratio calibration circuit and enlarging the calibration range of the clock duty ratio calibration circuit are achieved.

Description

technical field [0001] The present application relates to the technical field of signal processing, in particular to a clock duty ratio calibration circuit. Background technique [0002] In circuits such as double data rate synchronous dynamic random access memory (DDR SDRAM), pipelined analog-to-digital converter (Pipelined ADC) and phase-locked loop (PLL), a clock with a 50% clock duty cycle can maximize Improve the utilization efficiency of the clock level, so as to ensure the normal operation of the system and the best performance. However, with the increase of the clock frequency in these systems, the clock signal is more and more susceptible to the fluctuation and noise of the process temperature and voltage during the propagation process, resulting in a duty cycle imbalance, which makes the input clock signal deviate from the ideal 50% duty cycle. The duty cycle calibration circuit is a kind of circuit designed to solve this problem. [0003] For pipeline ADC, in or...

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Problems solved by technology

[0006] The embodiment of the present application provides a clock duty cycle calibration circuit to at least solve the problems of low accuracy and narrow calibration range of the clock duty cycle calibration circuit in the related art

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