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Storage unit and manufacturing method thereof

A technology of storage unit and manufacturing method, which is applied in semiconductor/solid-state device manufacturing, electrical components, semiconductor devices, etc., can solve problems such as insufficient structural stability, and achieve the effect of reducing device size and increasing arrangement density

Active Publication Date: 2022-06-24
CHANGXIN MEMORY TECH INC
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

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Problems solved by technology

[0005] The purpose of the present disclosure is to provide a memory cell and its manufacturing method, which are used to overcome at least to some extent the problem of insufficient structural stability of vertical capacitors in the case of high-density arrangement due to the limitations and defects of related technologies

Method used

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  • Storage unit and manufacturing method thereof
  • Storage unit and manufacturing method thereof
  • Storage unit and manufacturing method thereof

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Embodiment Construction

[0042] Example embodiments will now be described more fully with reference to the accompanying drawings. Example embodiments, however, can be embodied in various forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the concept of example embodiments to those skilled in the art. The described features, structures, or characteristics may be combined in any suitable manner in one or more embodiments. In the following description, numerous specific details are provided in order to give a thorough understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of the specific details, or other methods, components, devices, steps, etc. may be employed. In other instances, well-known solutions have not been...

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Abstract

The present disclosure provides a memory unit and a manufacturing method thereof. The memory unit includes: a vertical transistor partially disposed in a substrate, the vertical transistor is provided with a source, a gate, and a drain from bottom to top, and the gate is connected to a word line, the source is connected to the bit line; the storage contact structure includes: a buried part, located in the first groove, the side of the first groove is wrapped by the isolation structure, and the lower surface of the buried part is connected to the vertical transistor Drain; protruding part, located on the buried part and connected to the upper surface of the buried part, the protruding part is a columnar structure; storage capacitor, with a lower plate, a dielectric layer, and an upper plate, the The lower pole plate is attached to the side surface of the protrusion, the dielectric layer is attached to the lower pole plate and the upper surface of the protrusion, and the upper pole plate is attached to the dielectric layer. The embodiments of the present disclosure can improve the structural strength and arrangement density of the memory cells.

Description

technical field [0001] The present disclosure relates to the technical field of integrated circuit manufacturing, and in particular, to a memory cell and a manufacturing method thereof. Background technique [0002] With the development of the integrated circuit manufacturing process, the device size is getting smaller and the arrangement density is increasing, which poses a huge challenge to the manufacturing process. [0003] In the DRAM manufacturing process, vertical memory cells (composed of vertical transistors and vertical capacitors) have become a new technology to increase the number of memory cells per unit area. In a vertical memory cell, the source, gate, and drain of the transistor are arranged in sequence from bottom to top, the storage capacitor is located above the drain of the transistor, and the lower plate of the capacitor is connected to the transistor through a storage contact structure (Stock NodeContact, SNC). Drain connection. As the transistor size...

Claims

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Application Information

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Patent Type & Authority Patents(China)
IPC IPC(8): H01L27/108H01L21/8242
CPCH10B12/02H10B12/30
Inventor 吴公一
Owner CHANGXIN MEMORY TECH INC