Patterning method and semiconductor structure

Abstract

Embodiments of the invention provide a patterning method and a semiconductor structure. The method comprises the following steps: providing a substrate which comprises a storage region and a peripheral circuit region which are adjacent to each other; forming a pattern transfer layer with a plurality of first hard masks on the substrate, wherein the first hard masks extend in the first direction and are arranged at intervals; forming a barrier layer on the pattern transfer layer; forming a plurality of second hard masks extending along a second direction on the barrier layer, wherein the second hard masks are arranged at intervals, and the second hard masks are located on the storage area and have structural defects at positions close to the peripheral circuit area; forming a first buffer layer on the barrier layer, and filling the first buffer layer with a second hard mask with structural defects, wherein the orthographic projection of the first buffer layer coincides with the peripheral circuit area and a part of the storage area; and patterning the barrier layer and the pattern transfer layer by taking the first buffer layer and the second hard mask which is not filled with the first buffer layer as masks.

Description

technical field [0001] The present invention relates to the technical field of semiconductors, in particular to a patterning method and a semiconductor structure. Background technique [0002] A dynamic random access memory (DRAM) includes an array area composed of a plurality of memory cells, and a peripheral area where a control circuit is located. With the continuous reduction of the size of semiconductor devices, in order to improve the integration of devices, a double patterning process (self-aligned-doubled patterning, SADP) is proposed. [0003] In the double patterning method of the prior art, due to the structural difference between the storage area and the peripheral circuit area, different etching load effects will be generated during the patterning process, resulting in misalignment of critical dimensions after patterning, which in turn causes the storage area Structural defects are generated at portions close to the peripheral circuit region. Therefore, how to...

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Problems solved by technology

[0003] In the double patterning method of the prior art, due to the structural difference between the storage area and the peripheral circuit area, different etching load effects will be generated during the patterning process, resulting in misalignment of critical dimensions after patterning, which in turn causes the storage area Structural defects occur near the peripheral circuit area

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