Clock recovery circuit and method, data processing chip and electronic equipment

Abstract

The invention discloses a clock recovery circuit and method, a data processing chip and electronic equipment. The clock recovery circuit comprises a latch module, a monostable module and an anti-phase logic unit, wherein a first setting end S of the latch module inputs multiple groups of pulse signals, and when any group of pulse signals jumps from a low level to a high level, a latch rises and is output through a first output end; the input end of the anti-phase logic unit is coupled with the first output end of the latch module, the first output end of the anti-phase logic unit is coupled with the first reset end RN of the latch module, and the second output end of the anti-phase logic unit is coupled with the second set end SN of the latch module; the first input end of the monostable module is coupled with the first output end of the anti-phase logic unit , the second input end of the monostable module inputs a voltage power supply, and the output end of the monostable module is coupled with the second reset end R of the latch module; and the input signal of the first reset end RN is opposite to the input signal of the second reset end R. According to the scheme, accurate clock recovery can be realized.

Description

technical field [0001] The invention relates to the field of circuit technology, in particular to a clock recovery circuit and method, a data processing chip, and electronic equipment. Background technique [0002] The purpose of clock recovery is to track the clock drift and part of the jitter at the sending end to determine correct data sampling. A clock recovery circuit (Clock Data Recovery, CDR) is usually implemented by means of a phase locked loop (phase lock loop, PLL) circuit. [0003] However, the accuracy of the clock signal recovered by the existing clock recovery circuit is low. Contents of the invention [0004] The embodiment of the present invention solves the technical problem that the accuracy of the clock signal recovered by the clock recovery circuit is low. [0005] In order to solve the above technical problems, an embodiment of the present invention provides a clock recovery circuit, which is applied to C-PHY, including: a latch module, a monostable...

AI Technical Summary

Problems solved by technology

[0003] However, the accuracy of the clock signal recovered by the existing clock recovery circuit is low

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