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Method and circuit for reducing cache access power consumption

A power consumption and circuit technology, applied in the direction of electrical digital data processing, instruments, digital data processing components, etc., can solve the problems of high power consumption and high power consumption, and achieve the effect of reducing power consumption

Pending Publication Date: 2021-07-20
ACTIONS ZHUHAI TECH CO
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  • Summary
  • Abstract
  • Description
  • Claims
  • Application Information

AI Technical Summary

Problems solved by technology

The second method is more friendly to software development and is a commonly used method at present, but the power consumption of accessing cache is higher than that of accessing RAM.
A way is a piece of RAM, which is equivalent to accessing multiple pieces of RAM at the same time, so the power consumption is higher than that of accessing a single piece of RAM

Method used

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  • Method and circuit for reducing cache access power consumption
  • Method and circuit for reducing cache access power consumption
  • Method and circuit for reducing cache access power consumption

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Embodiment Construction

[0030] The application will be further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described here are only used to explain related inventions, rather than to limit the invention. It should also be noted that, for the convenience of description, only the parts related to the related invention are shown in the drawings.

[0031] It should be noted that, in the case of no conflict, the embodiments in the present application and the features in the embodiments can be combined with each other. The present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments. The sequence of the steps in the following embodiments is only listed and can be adjusted if there is no conflict.

[0032] like figure 1 As shown, a method for reducing cache access power consumption provided by an embodiment of the present invention i...

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PUM

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Abstract

The embodiment of the invention provides a method for reducing cache access power consumption, and the method comprises the following steps that a CPU sends an access address for a cache access request, wherein the access address comprises an address high order and an address low order; a comparison controller compares the address high-order with a high-order cache address in an address register; if the comparison result is consistent, the CPU directly accesses the RAM corresponding to the high-level cache address. Meanwhile, the invention correspondingly provides a circuit for reducing the cache access power consumption, and the cache access power consumption can be effectively reduced.

Description

technical field [0001] The present application relates to circuits, in particular to a method and circuit for reducing cache access power consumption. Background technique [0002] In an SOC (System on Chip, system on chip) system, the CPU accesses the external storage medium at a relatively slow speed. For example, on a Bluetooth audio IC, the CPU generally uses SPI (Serial Peripheral Interface, Serial Peripheral Interface) NORFLASH as the storage medium, and the speed is generally not higher than 50MB / s, which is quite different from the bus interface speed of the CPU. Prior art generally has two kinds of methods to improve the execution efficiency of CPU: the one, use internal RAM to cache data, and the data exchange of internal RAM and external storage medium needs software operation; The 2nd, use cache (high-speed cache memory) to cache data, The data exchange between cache and external storage medium is done by hardware and is transparent to software. The second meth...

Claims

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Application Information

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IPC IPC(8): G06F1/3234
CPCG06F1/3275G06F1/3243
Inventor 周悦峰牟刚
Owner ACTIONS ZHUHAI TECH CO