Chip mounting process capable for reducing stress

Abstract

The invention provides a chip mounting process for reducing stress. The process comprises the following steps of S1, mounting a chip on the surface of a substrate through a surface mounting process, and performing reflow soldering to correspondingly connect each solder ball on the front surface of the chip with a bonding pad on the substrate, wherein the chip is provided with array type small chip units in advance; S2, filling the bottom of the chip with underfill glue, absorbing the liquid underfill glue to enter a gap between the chip and the substrate through the surface tension of the chip and the substrate, and then curing the underfill glue; S3, segmenting the back surface of the chip to form a groove, and segmenting the chip into the array type small chip units, wherein the small chip units realize the interconnection among the array type small chip units through the bonding pads and wires on the substrate. According to the invention, the chip is designed into an array structure, the chip is welded with the substrate and is divided into the array small chip units, so that the chip mounting consistency difficulty can be reduced, the mounting cost is reduced, and the total area of the chip is kept basically unchanged.

Description

technical field [0001] The invention relates to the technical field of semiconductors, in particular to a stress-reducing chip mounting process. Background technique [0002] Integrated circuit terminals are increasingly developing towards large-size chips. These two areas will have the following problems in terminal packaging and interconnection technologies: First, large-size chips will be subject to stress from the base during surface mounting. In the high and low temperature failure test, the large-size chip has a different thermal expansion coefficient from the base, which often leads to the breakage of the interconnection solder balls. If it is a three-dimensional package, then the adapter board between the chip and the base will break. ; Because flexible circuits need to match various usage environments, for wearable flexible circuits, if the size of the chip mounted on it is too large, it cannot be folded or bent at certain angles, which seriously affects the range o...

AI Technical Summary

Problems solved by technology

[0002] Integrated circuit terminals are increasingly developing towards large-size chips. These two areas will have the following problems in terminal packaging and interconnection technologies: First, large-size chips will be subject to stress from the base during surface mounting. In the high and low temperature failure test, the large-size chip has a different thermal expansion coefficient from the base, which often leads to the breakage of the interconnection solder balls. If it is a three-dimensional package, then the adapter plate between the chip and the base will break. ;Flexible circuits need to match various usage environments. For wearable flexible circuits, if the size of the chip mounted on it is too large, it cannot be folded or bent at certain angles, which seriously affects the range of use of the terminal.

[0003] At present, in order to achieve high integration of some applications in the industry, it is necessary to mount arrayed small chips to replace the large chips that were originally to be mounted. This not only increases the difficulty of consistency between chips, but also increases the number of mounting times and mounting costs. , also increases the overall chip area

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